diff options
| author | Keith Hui <buurin@gmail.com> | 2017-12-04 00:05:56 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-09 16:54:44 +0000 |
| commit | a8380fcfd80cca6ac88be5ac342e85c94d77ad7a (patch) | |
| tree | 5debac3ea25c56b242c3e68f6d2322e679587696 /src/soc/intel/skylake/finalize.c | |
| parent | ea8de493ff2113ba6170601bf0fa95451ecbffc5 (diff) | |
intel/i440bx: Correct RAM init programming
Corrects MBSC/MBFS programming when initializing DRAM on boards with both
3 and 4 DIMM slots.
Reformats comments to current coreboot standards.
Drops some romcc "optimizations" no longer necessary.
Boot tested on asus/p2b-ls, where it fixes a memory related hang after
SeaBIOS resets the board with nothing to boot from.
Change-Id: Ib8c21489338643e13f69bd58008d14733796d4d0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/finalize.c')
0 files changed, 0 insertions, 0 deletions