intel/skylake: More UPD params are added for PCH policy in FSP

Some more PCH Policy UPD Parameters are added in FSP.
Lockdown config moved from FSP to coreboot.
Removing settings in devicetree.cb which are zero.

BRANCH=none
BUG=none
TEST=Build and booted on kunimitsu, verified that CB is doing
  the Lockdowns which were previously done by FSP.

CQ-DEPEND=CL:*237842, CL:310191

Change-Id: I3dcf3a5340f3c5ef2fece2de5390cde48db4d327
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8bdb35897b640d271adcaed266030367f060553
Original-Change-Id: Ia201672565c07b2e03d972b2718512cd4fcbb95c
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310869
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12941
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)

1 files changed, 62 insertions, 8 deletions

diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index a382702ba0..e2577aadeb 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -16,12 +16,14 @@
 
 #include <arch/io.h>
 #include <bootstate.h>
+#include <chip.h>
 #include <console/console.h>
 #include <console/post_codes.h>
 #include <cpu/x86/smm.h>
 #include <reg_script.h>
 #include <spi-generic.h>
 #include <stdlib.h>
+#include <soc/lpc.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr.h>
 #include <soc/pm.h>
@@ -35,7 +37,6 @@ static void pch_finalize_script(void)
 	device_t dev;
 	uint32_t reg32, hsfs;
 	void *spibar = get_spi_bar();
-	u8 reg8;
 	u16 tcobase;
 	u16 tcocnt;
 	uint8_t *pmcbase;
@@ -51,19 +52,14 @@ static void pch_finalize_script(void)
 	hsfs |= SPIBAR_HSFS_FLOCKDN;
 	write32(spibar + SPIBAR_HSFS, hsfs);
 
-	/*TCO Lock down*/
+	/*TCO Lock down */
 	tcobase = pmc_tco_regs();
 	tcocnt = inw(tcobase + TCO1_CNT);
 	tcocnt |= TCO_LOCK;
 	outw(tcocnt, tcobase + TCO1_CNT);
 
-	/* Global SMI Lock */
-	dev = PCH_DEV_PMC;
-	reg8 = pci_read_config8(dev, GEN_PMCON_A);
-	reg8 |= SMI_LOCK;
-	pci_write_config8(dev, GEN_PMCON_A, reg8);
-
 	/* Lock down ABASE and sleep stretching policy */
+	dev = PCH_DEV_PMC;
 	reg32 = pci_read_config32(dev, GEN_PMCON_B);
 	reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
 	pci_write_config32(dev, GEN_PMCON_B, reg32);
@@ -75,11 +71,69 @@ static void pch_finalize_script(void)
 	write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
 }
 
+static void soc_lockdown(void)
+{
+	u8 reg8;
+	device_t dev;
+	const struct device *dev1 = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct soc_intel_skylake_config *config = dev1->chip_info;
+
+	/* Global SMI Lock */
+	if (config->LockDownConfigGlobalSmi == 0) {
+		dev = PCH_DEV_PMC;
+		reg8 = pci_read_config8(dev, GEN_PMCON_A);
+		reg8 |= SMI_LOCK;
+		pci_write_config8(dev, GEN_PMCON_A, reg8);
+	}
+
+	/* Bios Interface Lock */
+	if (config->LockDownConfigBiosInterface == 0) {
+		pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
+				  pci_read_config8(PCH_DEV_LPC,
+						   BIOS_CNTL) | LPC_BC_BILD);
+		/* Reads back for posted write to take effect */
+		pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
+		pci_write_config32(PCH_DEV_SPI, SPIBAR_BIOS_CNTL,
+				   pci_read_config32(PCH_DEV_SPI,
+						     SPIBAR_BIOS_CNTL) |
+				   SPIBAR_BC_BILD);
+		/* Reads back for posted write to take effect */
+		pci_read_config32(PCH_DEV_SPI, SPIBAR_BIOS_CNTL);
+		/* GCS reg of DMI */
+		pcr_andthenor8(PID_DMI, R_PCH_PCR_DMI_GCS, 0xFF,
+			       B_PCH_PCR_DMI_GCS_BILD);
+	}
+
+	/* Bios Lock */
+	if (config->LockDownConfigBiosLock == 0) {
+		pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
+				  pci_read_config8(PCH_DEV_LPC,
+						   BIOS_CNTL) | LPC_BC_LE);
+		pci_write_config8(PCH_DEV_SPI, BIOS_CNTL,
+				  pci_read_config8(PCH_DEV_SPI,
+						   BIOS_CNTL) | SPIBAR_BC_LE);
+	}
+
+	/* SPIEiss */
+	if (config->LockDownConfigSpiEiss == 0) {
+		pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
+				  pci_read_config8(PCH_DEV_LPC,
+						   BIOS_CNTL) | LPC_BC_EISS);
+		pci_write_config8(PCH_DEV_SPI, BIOS_CNTL,
+				  pci_read_config8(PCH_DEV_SPI,
+						   SPIBAR_BIOS_CNTL) |
+				  SPIBAR_BC_EISS);
+	}
+}
+
 static void soc_finalize(void *unused)
 {
 	printk(BIOS_DEBUG, "Finalizing chipset.\n");
+
 	pch_finalize_script();
 
+	soc_lockdown();
+
 	/* Indicate finalize step with post code */
 	post_code(POST_OS_BOOT);
 }