soc/intel/skylake: switch to common ACPI code

Use the common ACPI code to reduce code duplication.

After this change, `PSS_MAX_ENTRIES` is honored correctly in P-state
table generation (as of commit c2540a9) and the number reduces from 10
to 7 entries.

Also, remnants of P_BLK support missed in CB:58096 will vanish.

Tested on google/fizz: no errors in dmesg, ACPI tables remain the same
(except PSS, as mentioned above).

Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

1 files changed, 2 insertions, 55 deletions

diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c
index 61e9417abd..774dd5e1f5 100644
--- a/src/soc/intel/skylake/fadt.c
+++ b/src/soc/intel/skylake/fadt.c
@@ -2,68 +2,28 @@
 
 #include <acpi/acpi.h>
 #include <cpu/x86/smm.h>
-#include <soc/acpi.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
 #include "chip.h"
 
-void acpi_fill_fadt(acpi_fadt_t *fadt)
+void soc_fill_fadt(acpi_fadt_t *fadt)
 {
 	const uint16_t pmbase = ACPI_BASE_ADDRESS;
 	config_t *config = config_of_soc();
 
-	fadt->header.revision = get_acpi_table_revision(FADT);
-
-	fadt->sci_int = acpi_sci_irq();
-
-	if (permanent_smi_handler()) {
-		fadt->smi_cmd = APM_CNT;
-		fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
-		fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
-	}
-
-	fadt->pm1a_evt_blk = pmbase + PM1_STS;
-	fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
 	fadt->pm2_cnt_blk = pmbase + PM2_CNT;
 	fadt->pm_tmr_blk = pmbase + PM1_TMR;
-	fadt->gpe0_blk = pmbase + GPE0_STS(0);
 
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
 	fadt->pm2_cnt_len = 1;
 	fadt->pm_tmr_len = 4;
-	/* There are 4 GPE0 STS/EN pairs each 32 bits wide. */
-	fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
-	fadt->day_alrm = 0xd;
-	fadt->mon_alrm = 0x00;
+
 	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE;
 	if (!CONFIG(NO_FADT_8042))
 		fadt->iapc_boot_arch |= ACPI_FADT_8042;
 
-	fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
-			ACPI_FADT_SLEEP_BUTTON |
-			ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE;
-
-	if (CONFIG(USE_PM_ACPI_TIMER))
-		fadt->flags |= ACPI_FADT_PLATFORM_CLOCK;
-
 	if (config->s0ix_enable)
 		fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 
-	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
-	fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
-	fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
 	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
 	fadt->x_pm2_cnt_blk.bit_offset = 0;
@@ -77,17 +37,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 	fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
 	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-	/*
-	 * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5.
-	 * The bit_width field intentionally overflows here.
-	 * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which
-	 * seems to work fine on Linux 5.0 and Windows 10.
-	 */
-	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
-	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
-	fadt->x_gpe0_blk.addrh = 0;
 }