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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-03-22 10:43:42 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-05-06 04:12:59 +0000
commit59a621abc70464352eaf540bd6cb896935b9ba72 (patch)
treefec081238c01e28e0d31733444ed7ec7d7695a61 /src/soc/intel/skylake/elog.c
parent6dc72022a5b8cfb0299e741b86d26b6a208838f1 (diff)
soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
TGL boards using the Type-C subsystem for USB Type-C ports without a retimer attached may require a DC bias on the aux lines for certain modes to work. This patch adds native coreboot support for programming the IOM to handle this DC bias via a simple devicetree setting. Previously a UPD was required to tell the FSP which GPIOs were used for the pullup and pulldown biases, but the API for this UPD was effectively undocumented. BUG=b:174116646 TEST=Verified on volteer2 that a Type-C flash drive is enumerated succesfully on all ports. Verified all major power flows (boot, reboot, powerdown and S0ix/suspend) still work as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/elog.c')
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