diff options
| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2017-06-22 17:51:33 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-06-23 16:26:42 +0000 |
| commit | a6381d63d539e9485ad48970369b85633efeb847 (patch) | |
| tree | 54e28e1bac504245dcb94629e5d763d2f0e86175 /src/soc/intel/skylake/cpu.c | |
| parent | 73273860516721f917358ad620f7fbc771ca9430 (diff) | |
soc/intel/skylake: Remove post SMM Relocation uCode loading
As per latest BWG, ucode reloading should be done at the end
of Mp Init, i.e., after PRMRR and other features are enabled.
No reloading specifically after SMM Relocation is required.
As, in the Common CPU MP Init code, we are already doing a
uCode load at the end of MP Init Feature Programming, hence,
the uCode loading after SMM relocation can be removed.
Change-Id: Ib1957c5fe5a8c83bb20b978a9841670b0c3e8846
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/cpu.c')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 21 |
1 files changed, 1 insertions, 20 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index f3bd99508d..e3be73870f 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -46,20 +46,6 @@ #include <soc/smm.h> #include <soc/systemagent.h> -/* - * TODO: This Global variable must be removed once the following - * two cases are resolved - - * - * 1) SGX enabling for the BSP issue gets solved, due to which - * configure_sgx() function is kept inside soc_init_cpus(). - * 2) uCode loading after SMM relocation is deleted inside - * per_cpu_smm_trigger() function, since as per - * current BWG, uCode loading can be done after all feature - * programmings are done. There is no specific recommendation - * to do it after SMM Relocation. - */ -static const void *microcode_patch; - /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -453,9 +439,6 @@ static void per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - intel_microcode_load_unlocked(microcode_patch); } static void post_mp_init(void) @@ -494,8 +477,6 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus, const void *microcode) { - microcode_patch = microcode; - if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); @@ -508,7 +489,7 @@ void soc_init_cpus(struct bus *cpu_bus, const void *microcode) * here to get SGX enabled on BSP. This behavior needs to root-caused * and we shall not have this redundant call. */ - configure_sgx(microcode_patch); + configure_sgx(microcode); } int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) |