Skylake: Support Intel Speed Shift Technology based on config

Intel Speed Shift Technology is a new mechanism that replaces
Legacy P-state. ISST allows OS hints about energy/performance
preference. H/W performs the actual P-state control (autonomous)

1. Optimization frequency seclection for low residency workloads,
no longer a static knee point.
2. Optimized frequency selection for best energy to performance
trade offs.
3. Kick down frequency (from idle) fpr best responsiveness while
taking energy consumption init account.

Coreboot's responsiblity is to configure MSR 0x1AA ISST_EN bits
which will reflect in CPUID.06h:EAX[Bit 7] that driver checkes
and enable HWP accordingly.

BUG=chrome-os-partner:47517
BRANCH=None
TEST=Booted kunimitsu and verify HWP getting enabled/disabled
using Intel P-state driver.

Change-Id: I91722aa1077f4ef6c8620b103be3e29cfcd974e5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: aa7d004cb2e19047e4434e3e2544cf69393ce28f
Original-Change-Id: Ie617da337babde7f196a7af712263e37f7eed56f
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313107
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://review.coreboot.org/13835
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 29 insertions, 0 deletions

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 2fa858257d..327bee90c3 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -207,6 +207,32 @@ static void configure_thermal_target(void)
 	}
 }
 
+static void configure_isst(void)
+{
+	device_t dev = SA_DEV_ROOT;
+	config_t *conf = dev->chip_info;
+	msr_t msr;
+
+	if (conf->speed_shift_enable) {
+		/*
+		* Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
+		  is supported or not. Coreboot needs to configure MSR 0x1AA
+		  which is then reflected in the CPUID register.
+		*/
+		msr = rdmsr(MSR_MISC_PWR_MGMT);
+		msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */
+		msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
+		msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */
+		wrmsr(MSR_MISC_PWR_MGMT, msr);
+	} else {
+		msr = rdmsr(MSR_MISC_PWR_MGMT);
+		msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */
+		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */
+		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */
+		wrmsr(MSR_MISC_PWR_MGMT, msr);
+	}
+}
+
 static void configure_misc(void)
 {
 	msr_t msr;
@@ -335,6 +361,9 @@ static void cpu_core_init(device_t cpu)
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();
 
+	/* Configure Intel Speed Shift */
+	configure_isst();
+
 	/* Thermal throttle activation offset */
 	configure_thermal_target();