diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-08-17 15:49:58 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-25 17:58:08 +0000 |
| commit | c204aaa23b8455457920a56a85b0128f9818f461 (patch) | |
| tree | aab5c43aae02df5f04ccea3d903a04d887012c9d /src/soc/intel/skylake/chip_fsp20.c | |
| parent | bcefbe163f70ef2590be252057d626e788047b16 (diff) | |
soc/intel/skylake: Add LPC and SPI lock down config option
This patch to provide new config options to perform LPC and SPI
lock down either by FSP or coreboot.
Remove EISS bit programming as well.
TEST=Build and boot Eve and Poppy.
Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/chip_fsp20.c')
| -rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index c5ecc97b01..aa612ede0a 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -201,7 +201,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SataEnable = config->EnableSata; params->SataMode = config->SataMode; tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; - tconfig->PchLockDownBiosInterface = config->LockDownConfigBiosInterface; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; /* * To disable HECI, the Psf needs to be left unlocked @@ -210,9 +209,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) * do the changes and then lock it back in coreboot during finalize. */ tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; - - params->PchLockDownBiosLock = config->LockDownConfigBiosLock; - params->PchLockDownSpiEiss = config->LockDownConfigSpiEiss; + if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + tconfig->PchLockDownBiosInterface = 0; + params->PchLockDownBiosLock = 0; + params->PchLockDownSpiEiss = 0; + /* + * Skip Spi Flash Lockdown from inside FSP. + * Making this config "0" means FSP won't set the FLOCKDN bit + * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). + * So, it becomes coreboot's responsibility to set this bit + * before end of POST for security concerns. + */ + params->SpiFlashCfgLockDown = 0; + } params->PchSubSystemVendorId = config->PchConfigSubSystemVendorId; params->PchSubSystemId = config->PchConfigSubSystemId; params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; @@ -248,15 +257,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->ShowSpiController = dev->enabled; /* - * Skip Spi Flash Lockdown from inside FSP. - * Making this config "0" means FSP won't set the FLOCKDN bit of - * SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). - * So, it becomes coreboot's responsibility to set this bit before - * end of POST for security concerns. - */ - params->SpiFlashCfgLockDown = config->SpiFlashCfgLockDown; - - /* * Send VR specific mailbox commands: * 000b - no VR specific command sent * 001b - VR mailbox command specifically for the MPS IMPV8 VR |