diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-02-03 18:57:49 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-02-14 19:13:03 +0100 |
| commit | a4b11e5c90a51dadc9b02ec080c0fb192cac3997 (patch) | |
| tree | 6770d18fbf8dfb9dbd0e85fffdc062b30bfd404d /src/soc/intel/skylake/chip_fsp20.c | |
| parent | 408fda799a55c4d104178dfa733b4ade2ad454cf (diff) | |
soc/intel/skylake: Perform CPU MP Init before FSP-S Init
As per BWG, CPU MP Init (loading ucode) should be done prior
to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry
(before FSP-S call).
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Boot to OS with all threads enabled.
Change-Id: Ia6f83d466fb27e1290da84abe7832dc814b5273a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18287
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/chip_fsp20.c')
| -rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 2aef65af29..9c87b65bbd 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2016-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -59,7 +59,7 @@ static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = &soc_init_cpus, + .init = DEVICE_NOOP, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, #endif |