diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-06-08 17:57:37 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-06-22 01:58:17 +0000 |
| commit | f699c14c03a78549b0e5ed32cf9714473127c618 (patch) | |
| tree | 681009836bbd6a92e49ffe3b9dc03145274ad38a /src/soc/intel/skylake/chip_fsp20.c | |
| parent | b775a62bb9fe07785b83767d58573937c5783bec (diff) | |
soc/intel/common/block/cpu: Add option to skip coreboot AP init
SoC users from IOTG team is looking forward for a solution to skip
coreboot AP initialization flow and make use of FSPS-UPD to
perform AP reset.
TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs
out of reset.
Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/chip_fsp20.c')
| -rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 00c7163a2f..a2bd16bd53 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -29,6 +29,7 @@ #include <device/pci_ids.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/chip.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <romstage_handoff.h> @@ -388,7 +389,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchSirqEnable = config->SerialIrqConfigSirqEnable; params->PchSirqMode = config->SerialIrqConfigSirqMode; - params->CpuConfig.Bits.SkipMpInit = !config->use_fsp_mp_init; + params->CpuConfig.Bits.SkipMpInit = !chip_get_fsp_mp_init(); for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++) params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; |