diff options
author | Subrata Banik <subrata.banik@intel.com> | 2018-05-28 16:12:03 +0530 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-06-07 21:58:19 +0000 |
commit | 9cd99a1524cd8c7cd6100cfc9d68e85eea5ac265 (patch) | |
tree | b5eaea43ae458551051d1f42d952603e60b98d49 /src/soc/intel/skylake/chip_fsp20.c | |
parent | 6994bfefb59304140e6b65d4d71e0719b104d257 (diff) |
soc/intel/common/pch: Add pch lockdown code
pch lockdown functionality can be used by supported PCH.
Right now pch lockdown functionality is applied for SPT
(Skylake SOC) and CNP(Cannon Lake SOC) PCH.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL and CNL platform.
Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/chip_fsp20.c')
-rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index ebfad667bb..00c7163a2f 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -30,6 +30,7 @@ #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/xdci.h> +#include <intelpch/lockdown.h> #include <romstage_handoff.h> #include <soc/acpi.h> #include <soc/intel/common/vbt.h> @@ -211,14 +212,6 @@ static void soc_enable(struct device *dev) dev->ops = &cpu_bus_ops; } -static int get_lockdown_config(void) -{ - const struct soc_intel_common_config *soc_config; - soc_config = chip_get_common_soc_structure(); - - return soc_config->chipset_lockdown; -} - struct chip_operations soc_intel_skylake_ops = { CHIP_NAME("Intel 6th Gen") .enable_dev = &soc_enable, |