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authorSubrata Banik <subrata.banik@intel.com>2019-07-08 14:49:22 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-07-11 05:57:41 +0000
commit10a9432cc2ad77234442bd639194c5a80050854e (patch)
treece6f68feab9582d2ab62765cd0d9a3262bb62b69 /src/soc/intel/skylake/chip.h
parent5b9948140f97eceb47ba026d7bad6dfa2a3c483d (diff)
soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer
This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer for better code sharing. Also ported CB:33512 for SPT and ICP PCH. Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
-rw-r--r--src/soc/intel/skylake/chip.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 9c8e2bfaa9..da941dc643 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -513,9 +513,6 @@ struct soc_intel_skylake_config {
/* Enable/Disable host reads to PMC XRAM registers */
u8 PchPmPmcReadDisable;
- /* Statically clock gate 8254 PIT. */
- u8 clock_gate_8254;
-
/*
* Use SD card detect GPIO with default config:
* - Edge triggered