diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-08-07 22:29:42 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-14 15:20:10 +0200 |
| commit | 9a8dc37cdd9486926c6b5416dd48f4f075b2612d (patch) | |
| tree | 9ffb787910a9361d1024397c99ec7654a99a91af /src/soc/intel/skylake/chip.h | |
| parent | 799bf781fdc71baa2332fc75f2a382c15f2ce321 (diff) | |
skylake: provide GPE0 routing devicetree configuration
On skylake the GPE0 routing can be dynamically changed to
a particular GPIO group. Provide the ability for the mainboard
to set the route accordingly. If any of the values in the
devicetree are the same the current setting in the PMC register
is used. The GPIO communities need to have matching configuration
for the plumbing to work properly.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados w/ and w/o devicetree changes. Fields
are set accordingly.
Original-Change-Id: I263d648c8ea8a70b21570f01b333d05a5fa2a4e3
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291930
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I966d38bc197dbb52a2ba50927c06e243e169afbe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11203
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 96389a9471..873342ae47 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -19,14 +19,16 @@ * Foundation, Inc. */ + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + #include <stdint.h> +#include <soc/gpio_defs.h> #include <soc/pci_devs.h> #include <soc/pmc.h> #include <soc/serialio.h> -#ifndef _SOC_CHIP_H_ -#define _SOC_CHIP_H_ - struct soc_intel_skylake_config { /* * Interrupt Routing configuration @@ -42,10 +44,15 @@ struct soc_intel_skylake_config { uint8_t pirqh_routing; /* GPE configuration */ - uint32_t gpe0_en_1; - uint32_t gpe0_en_2; - uint32_t gpe0_en_3; - uint32_t gpe0_en_4; + uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ + uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ + uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ + uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ + /* Gpio group routed to each dword of the GPE0 block. Values are + * of the form GPP_[A:G] or GPD. */ + uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ /* GPIO SMI configuration */ uint32_t ec_smi_gpio; |