diff options
author | Shelley Chen <shchen@chromium.org> | 2017-06-29 11:31:16 -0700 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-14 22:47:25 +0000 |
commit | 20c3ea5c4f2c83df7c9416b2b9cbcff63e2c74f1 (patch) | |
tree | 4f53314fef60d9a75fea39ce13e76bd85e3f9c5b /src/soc/intel/skylake/chip.h | |
parent | 2a7fbea3f14cae2119816c5a28c455f45c75650f (diff) |
soc/intel/skylake: Set PsysPL2 MSR
BUG=b:7473486, b:35775024
BRANCH=None
TEST=On bootup make sure PL2 and PsysPL2 values set
properly (through debug output)
Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
-rw-r--r-- | src/soc/intel/skylake/chip.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index b4f6545c36..67a6783186 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -97,6 +97,9 @@ struct soc_intel_skylake_config { /* PL2 Override value in Watts */ u32 tdp_pl2_override; + /* SysPL2 Value in Watts */ + u32 tdp_psyspl2; + /* * The following fields come from FspUpdVpd.h. * These are configuration values that are passed to FSP during |