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authorMichael Niewöhner <foss@mniewoehner.de>2020-11-23 15:53:28 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-12-04 00:10:24 +0000
commit14512f9a9be08d945830ddb6d0e48f4d6fc1635c (patch)
treec8956704656524dd17be720079b8304149dd1620 /src/soc/intel/skylake/chip.h
parentc3ab442cc1e1b36ae647eed6158ad10c9c93d3e6 (diff)
soc/intel/common/block/gpio: add code for NMI enabling
Especially server boards, like the Supermicro X11SSM-F, often have a NMI button and NMI functionality that can be triggered via IPMI. The purpose of this is to cause the OS to create a system crashdump from a hang system or for debugging. Add code for enabling NMI interrupts on GPIOs configured with PAD_CFG_GPI_NMI. The enabling mechanism is the same as SMI, so the SMI function was copied and adapted. The `pad_community` struct gained two variables for the registers. Also register the NMI for LINT1 in the MADT in accordance to ACPI spec. Test: Linux detects the NMI correctly in dmesg: [ 0.053734] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
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