diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-03-31 14:02:47 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-04-06 00:45:36 +0200 |
| commit | 05a6f29d32c246569b7a0561d35ccbf49eec1fb8 (patch) | |
| tree | a0347e4edb13a2f3bebcbbf8745a4af0a5f18969 /src/soc/intel/skylake/chip.h | |
| parent | 108f87262bf47ce3549fa0c5ed16a40fe916656f (diff) | |
soc/intel/skylake: Add support for GSPI controller
Sky Lake PCH contains two GSPI controllers. Using the common GSPI
controller driver implementation for Intel PCH, add support for GSPI
controller buses on Sky Lake/Kaby Lake.
BUG=b:35583330
Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19099
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 85857d8200..ce5fe22b98 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -21,6 +21,7 @@ #include <arch/acpi_device.h> #include <device/i2c.h> +#include <intelblocks/gspi.h> #include <stdint.h> #include <soc/gpio_defs.h> #include <soc/gpe.h> @@ -208,6 +209,9 @@ struct soc_intel_skylake_config { enum skylake_i2c_voltage i2c_voltage[SKYLAKE_I2C_DEV_MAX]; struct lpss_i2c_bus_config i2c[SKYLAKE_I2C_DEV_MAX]; + /* GSPI */ + struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + /* Camera */ u8 Cio2Enable; u8 SaImguEnable; |