diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-09-04 13:53:14 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-10 09:47:57 +0000 |
| commit | 7fce30c2a5dd748ab3efa79fb24e3c85cef11628 (patch) | |
| tree | 12ff4714796da2da3dfd1cb5574df66d443fb8f2 /src/soc/intel/skylake/chip.h | |
| parent | c1bc8171e65bb9100c4e9cb0efe8e5aa9771d4d3 (diff) | |
skylake: Enable DPTF based on devicetree setting
Enable DPTF flag in ACPI NVS based on devicetree setting
for the mainboard.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glaods coreboot
Change-Id: I06ec6b050eb83c6a7ee1e48f2bd9f5920f7bfa51
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5728a8a37b1a50a483aa211563fb7ad312002ce5
Original-Change-Id: I08d61416c24b3c8857205cf88931f0bb2b38896c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297755
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 9b43b7fa2d..94aa3a4ea9 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -86,6 +86,9 @@ struct soc_intel_skylake_config { /* Enable S0iX support */ int s0ix_enable; + /* Enable DPTF support */ + int dptf_enable; + /* Deep SX enable for both AC and DC */ int deep_s3_enable; int deep_s5_enable; |