diff options
| author | Naresh G Solanki <naresh.solanki@intel.com> | 2016-08-30 20:47:13 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-19 21:32:22 +0200 |
| commit | a2d4062d427d18127707306dada5e79d69bd3691 (patch) | |
| tree | bcf9f53b1f1d74c9d04df6d42af2602ff97038b4 /src/soc/intel/skylake/chip.h | |
| parent | 21130c6508161ada1d28c90a4003c89afc3fd162 (diff) | |
soc/intel/skylake: Add FSP 2.0 support in ramstage
Add FSP 2.0 support in ramstage.
Populate required Fsp Silicon Init params and configure mainboard
specific GPIOs.
Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for
pre OS screens.
Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16592
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 62e28e693c..00393b2492 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -273,6 +273,19 @@ struct soc_intel_skylake_config { u16 PchConfigSubSystemVendorId; /* Subsystem ID of the PCH devices*/ u16 PchConfigSubSystemId; + + /* + * Determine if WLAN wake from Sx, corresponds to the + * HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + */ + u8 PchPmWoWlanEnable; + + /* + * Determine if WLAN wake from DeepSx, corresponds to + * the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. + */ + u8 PchPmWoWlanDeepSxEnable; + /* * Corresponds to the "WOL Enable Override" bit in the General PM * Configuration B (GEN_PMCON_B) register |