soc/intel/skylake: Add config for enabling LTR for PCIe Root port

There are a lot errors reported by AER driver for root port 0.
The erors are being caused by an unsupported request from the
device to the upstream port. Enabling LTR on the root port stops
these errors, it is because LTR is enabled on the device side but
not on the root port and hence root port was logging the LTR messages
from the device as unsupported.

The PCIe base spec (v3.1a) section 6.18 also states that:
LTR support is discovered and enabled through reporting and control
registers described in Chapter 7. Software must not enable LTR in an
Endpoint unless the Root Complex and all intermediate Switches indicate
support for LTR. Note that it is not required that all Endpoints support
LTR to permit enabling LTR in those Endpoints that do support it. When
enabling the LTR mechanism in a hierarchy, devices closest to the
Root Port must be enabled first.

If an LTR Message is received at a Downstream Port that does not
support LTR or if LTR is not enabled, the Message must be treated
as an Unsupported Request. FSP has a UPD for enabling/disabling
LTR on root port, use the same for configuring LTR on PCIe root ports.

BUG=b:65570878
TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported
     by AER driver for root port 0.

Change-Id: Ica97faa78fcd991dad63ae54d2ada82194b4202a
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 34 insertions, 1 deletions

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 45f3f9982a..606078b4a1 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -169,12 +169,45 @@ struct soc_intel_skylake_config {
 	/* DCI Enable/Disable */
 	u8 PchDciEn;
 
-	/* Pcie Root Ports */
+	/*
+	 * Pcie Root Port configuration:
+	 * each element of array corresponds to
+	 * respective PCIe root port.
+	 */
+
+	/*
+	 * Enable/Disable Root Port
+	 * 0: Disable Root Port
+	 * 1: Enable Root Port
+	 */
 	u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
+
+	/*
+	 * Enable/Disable Clk-req support for Root Port
+	 * 0: Disable Clk-Req
+	 * 1: Enable Clk-req
+	 */
 	u8 PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS];
+
+	/*
+	 * Clk-req source for Root Port
+	 */
 	u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS];
+
+	/*
+	 * Enable/Disable AER (Advanced Error Reporting) for Root Port
+	 * 0: Disable AER
+	 * 1: Enable AER
+	 */
 	u8 PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
 
+	/*
+	 * Enable/Disable Latency Tolerance Reporting for Root Port
+	 * 0: Disable LTR
+	 * 1: Enable LTR
+	 */
+	u8 PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
+
 	/* USB related */
 	struct usb2_port_config usb2_ports[16];
 	struct usb3_port_config usb3_ports[10];