diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2016-02-08 17:15:29 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-01 20:57:45 +0100 |
| commit | b7e69a2e561d557a7d243a15d91a5cede56e5eb8 (patch) | |
| tree | ba1b11d955e902083f29cee10bb04b72af419567 /src/soc/intel/skylake/chip.h | |
| parent | 2a696c07b9cdcd484800596fb850f95260419d11 (diff) | |
Skylake: Support Intel Speed Shift Technology based on config
Intel Speed Shift Technology is a new mechanism that replaces
Legacy P-state. ISST allows OS hints about energy/performance
preference. H/W performs the actual P-state control (autonomous)
1. Optimization frequency seclection for low residency workloads,
no longer a static knee point.
2. Optimized frequency selection for best energy to performance
trade offs.
3. Kick down frequency (from idle) fpr best responsiveness while
taking energy consumption init account.
Coreboot's responsiblity is to configure MSR 0x1AA ISST_EN bits
which will reflect in CPUID.06h:EAX[Bit 7] that driver checkes
and enable HWP accordingly.
BUG=chrome-os-partner:47517
BRANCH=None
TEST=Booted kunimitsu and verify HWP getting enabled/disabled
using Intel P-state driver.
Change-Id: I91722aa1077f4ef6c8620b103be3e29cfcd974e5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: aa7d004cb2e19047e4434e3e2544cf69393ce28f
Original-Change-Id: Ie617da337babde7f196a7af712263e37f7eed56f
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313107
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://review.coreboot.org/13835
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 0b87f2d08e..6203916088 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -326,6 +326,8 @@ struct soc_intel_skylake_config { /* PL2 Override value in Watts */ u32 tdp_pl2_override; u8 PmTimerDisabled; + /* Intel Speed Shift Technology */ + u8 speed_shift_enable; }; typedef struct soc_intel_skylake_config config_t; |