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| author | Benjamin Doron <benjamin.doron00@gmail.com> | 2020-03-14 01:53:25 +0000 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-15 00:01:05 +0000 |
| commit | adcb870837518283fac6eac24a628d42912fd4a3 (patch) | |
| tree | 453779d2c48fc8da110e8e633319f1b62ce45ac5 /src/soc/intel/skylake/chip.c | |
| parent | 3e314636a63e5f981eb038a2767bd606fea9f468 (diff) | |
soc/intel/skylake: Configure L1 substates for PCH root ports
Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration.
Tested on an Acer Aspire VN7-572G (Skylake-U).
Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/skylake/chip.c')
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index dfbdfb812d..4139570f64 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -212,6 +212,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; if (config->PcieRpAspm[i]) params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1; + if (config->pcie_rp_l1substates[i]) + params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1; } /* |