diff options
| author | Archana Patni <archana.patni@intel.com> | 2015-11-11 01:29:23 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-17 22:54:17 +0100 |
| commit | 7846e34c02473a2a000e1fda1e2051475ef3fbf1 (patch) | |
| tree | dba3417a968fa94dd241cbcd85be65eb5975b9fb /src/soc/intel/skylake/chip.c | |
| parent | df13c31ed6fdad2cdb6e8e874f26e5cad2ce935f (diff) | |
intel/skylake: disable heci1 if psf is unlocked
This patch adds support for disabling the heci1 device
at the end of boot sequence. Prior to this, FSP would have
sent the end of post message to ME and initiated the d0i3 bit.
This uses the Psf unlock policy and the p2sb device to disable
the heci1 device, then lock the configuration and hide the device.
BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for kunimitsu or glados board. set the hecienabled policy
to 0 and check for heci 1 device status in kernel lspci.
CQ-DEPEND=CL:*238451
Change-Id: I26b145231f8ed0c140af42d378b222e857d9aff6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fe184b8baf1bea9bcd0af1841785a4d763af9358
Original-Change-Id: I3b435491aeea0f2ca36b7877e942dc940560e4dd
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311912
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12976
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/chip.c')
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index e6eb537fc5..f4dc4a729f 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -347,6 +347,18 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->SkipMpInit = config->SkipMpInit; + /* + * To disable Heci, the Psf needs to be left unlocked + * by FSP after end of post sequence. Based on the devicetree + * setting, we set the appropriate PsfUnlock policy in Fsp, + * do the changes and then lock it back in Coreboot + * + */ + if (config->HeciEnabled == 0) + params->PsfUnlock = 1; + else + params->PsfUnlock = 0; + for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) { params->VrConfigEnable[i] = config->domain_vr_config[i].vr_config_enable; |