diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2015-11-19 16:27:03 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-16 11:56:26 +0100 |
| commit | b6319c1121332551a51a9ef7d88c3e7ed8d0670d (patch) | |
| tree | 749afd392a34b0072bb68f03d47ad70ecc123df8 /src/soc/intel/skylake/chip.c | |
| parent | 19d9fe9ebc81478b9e7074e9ed6fa8f2070f0004 (diff) | |
intel/skylake: Enable SkipMpInit token
This patch helps to enable SkipMpInit token of FSP SiliconInit UPD
BRANCH=none
BUG=chrome-os-partner:44805
TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB.
CQ-DEPEND=CL:310869
Change-Id: I43377e4b8adadf42091a9387883363fdfbab4c1b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b7962273fd1a591cfe9a658f49ebc7d23bcad577
Original-Change-Id: I977d2d39c283d74f1aa9033c8aa60dc652735019
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310192
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12943
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/chip.c')
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 951e461ee1..ec5128a50c 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -345,6 +345,8 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->SerialIrqConfigSirqMode = config->SerialIrqConfigSirqMode; params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse; + params->SkipMpInit = config->SkipMpInit; + /* Show SPI controller if enabled in devicetree.cb */ dev = dev_find_slot(0, PCH_DEVFN_SPI); params->ShowSpiController = dev->enabled; |