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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2016-10-29 21:48:18 +0200
committerRonald G. Minnich <rminnich@gmail.com>2016-11-07 16:47:11 +0100
commit7ca9b8ae5014a745855296903682ae803235cb35 (patch)
tree28abfebb29b7e6666f7794923d7ea7c095bfb891 /src/soc/intel/skylake/bootblock
parent7d9068fe0b5d87fe3fe075d5d9a5f7493f5b1eac (diff)
mb/lowrisc/nexys4ddr: Actually fix the UART clock setup
Ron's code calculated the DLL and DLM registers of the 8250 UART, but that's the job of the UART driver. uart_input_clock_divider isn't needed anymore because the default value of 16 works. As a bonus, the baud rate can now be selected in Kconfig, instead of being hardcoded at 115200. TEST=Booted the board at 9600 and 115200 baud. Change-Id: I3d5e49568b798a6a6d944db1161def7d0a2d3b48 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17188 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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