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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-05-04 18:02:17 +0530
committerAaron Durbin <adurbin@chromium.org>2017-06-09 19:24:58 +0200
commit0a203d13f672b5cf12a56eaecfbcbe2e081f18ed (patch)
tree7d1d1e101e602102c528851769de3229095c2744 /src/soc/intel/skylake/bootblock
parent19b546f48cb790285afa366dceab9da62cbbe4ac (diff)
soc/intel/skylake: Use CPU common library code
This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19566 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
-rw-r--r--src/soc/intel/skylake/bootblock/cpu.c33
1 files changed, 7 insertions, 26 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index ee344efb13..4a5bf08042 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -14,18 +14,13 @@
* GNU General Public License for more details.
*/
-#include <arch/io.h>
-#include <console/console.h>
#include <cpu/x86/msr.h>
#include <delay.h>
+#include <intelblocks/cpulib.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/msr.h>
#include <reset.h>
#include <soc/bootblock.h>
-#include <soc/cpu.h>
-#include <soc/iomap.h>
-#include <soc/msr.h>
-#include <soc/pci_devs.h>
-#include <stdint.h>
/* Soft Reset Data Register Bit 12 = MAX Boot Frequency */
#define SPI_STRAP_MAX_FREQ (1<<12)
@@ -93,24 +88,10 @@ void bootblock_cpu_init(void)
void set_max_freq(void)
{
- msr_t msr, perf_ctl, platform_info;
-
- /* Check for configurable TDP option */
- platform_info = rdmsr(MSR_PLATFORM_INFO);
-
- if ((platform_info.hi >> 1) & 3) {
+ if (cpu_config_tdp_levels())
/* Set to nominal TDP ratio */
- msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
- perf_ctl.lo = (msr.lo & 0xff) << 8;
- } else {
- /* Platform Info bits 15:8 give max ratio */
- msr = rdmsr(MSR_PLATFORM_INFO);
- perf_ctl.lo = msr.lo & 0xff00;
- }
-
- perf_ctl.hi = 0;
- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
-
- printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
- ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
+ cpu_set_p_state_to_nominal_tdp_ratio();
+ else
+ /* Set to max non Turbo ratio */
+ cpu_set_p_state_to_max_non_turbo_ratio();
}