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authorRizwan Qureshi <rizwan.qureshi@intel.com>2016-08-04 20:01:12 +0530
committerMartin Roth <martinroth@google.com>2016-08-18 06:26:40 +0200
commitcf73c1317dd1ab62a96eb17ed6d9c8590fb4c514 (patch)
treee8b463fb1fed894b6d432b37028c549bf5829202 /src/soc/intel/skylake/bootblock
parent4a36c4e9fc66bf442f46e1e6d742b2d6c50a2ae1 (diff)
skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init
Prepare Skylake for FSP2.0 support. We do not use FSP-T in FSP2.0 driver, hence guard the FspTempRamInit call under a switch. In addition to the current early PCH configuration program few more register, so all in all we do the following, * Program and enable ACPI Base. * Program and enable PWRM Base. * Program TCO Base. * Program Interrupt configuration registers. * Program LPC IO decode range. * Program SMBUS Base address and enable it. * Enable upper 128 bytes of CMOS. And split the above programming into into smaller functions. Also, as part of bootblock_pch_early_init we enable decoding for HPET range. This is needed for FspMemoryInit to store and retrieve a global data pointer. And also move P2SB related definitions to a new header file. TEST=Build and boot Kunimitsu Change-Id: Ia201e03b745836ebb43b8d7cfc77550105c71d16 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16113 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
-rw-r--r--src/soc/intel/skylake/bootblock/bootblock.c11
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c9
2 files changed, 15 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index ab1720c83a..f644d1f638 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -14,7 +14,6 @@
*/
#include <bootblock_common.h>
-#include <fsp/bootblock.h>
#include <soc/bootblock.h>
#include <soc/romstage.h>
@@ -36,12 +35,14 @@ void bootblock_soc_early_init(void)
void bootblock_soc_init(void)
{
- /* locate and call FspTempRamInit */
- bootblock_fsp_temp_ram_init();
+ /* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */
+ if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))
+ bootblock_fsp_temp_ram_init();
+
/*
* Perform early chipset initialization before fsp memory init
- * example: pirq->irq programming, enabling smbus, pmcbase, abase,
- * get platform info, i2c programming
+ * example: pirq->irq programming, enabling smbus, set pmcbase
+ * and abase, i2c programming and print platform info
*/
report_platform_info();
set_max_freq();
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 569611502e..e7f414b721 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -18,6 +18,7 @@
#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
+#include <soc/p2sb.h>
#include <soc/pci_devs.h>
#include <soc/pcr.h>
#include <soc/spi.h>
@@ -64,6 +65,14 @@ static void enable_p2sbbar(void)
/* Enable P2SB MSE */
pci_write_config8(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+ /*
+ * Enable decoding for HPET memory address range.
+ * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
+ * the High Performance Timer memory address range
+ * selected by bits 1:0
+ */
+ pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);
}
void bootblock_pch_early_init(void)