summaryrefslogtreecommitdiff
path: root/src/soc/intel/skylake/bootblock
diff options
context:
space:
mode:
authorLee Leahy <leroy.p.leahy@intel.com>2017-03-16 16:44:36 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2017-03-17 02:34:52 +0100
commitb439a929392ba54dee43455f6e164b884cb8c308 (patch)
treeffc44834d8ff6144d360a356dab0688e006945af /src/soc/intel/skylake/bootblock
parent573564cca8cd01cadf179546b8b124694fd3dcbb (diff)
soc/intel/skylake: Wrap lines at 80 columns
Fix the following warning detected by checkpatch: WARNING: line over 80 characters TEST=Build for glados Change-Id: I79341f46ca06ac052f987975ccaf975470d27806 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18867 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
-rw-r--r--src/soc/intel/skylake/bootblock/cache_as_ram.S4
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S
index 3f8f0f0fb9..eb3d390154 100644
--- a/src/soc/intel/skylake/bootblock/cache_as_ram.S
+++ b/src/soc/intel/skylake/bootblock/cache_as_ram.S
@@ -249,8 +249,8 @@ find_llc_subleaf:
* Ensure region to cache meets MTRR requirements for
* size and alignment.
*/
- movl $(0xFFFFFFFF - CONFIG_ROM_SIZE + 1), %edi /* Code region base */
- movl $CONFIG_ROM_SIZE, %eax /* Code region size */
+ movl $(0xFFFFFFFF - CONFIG_ROM_SIZE + 1), %edi /* Code region base */
+ movl $CONFIG_ROM_SIZE, %eax /* Code region size */
cmpl $0, %edi
jz .halt_forever
cmpl $0, %eax
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 6279cf2b6d..07beae8f9e 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -192,8 +192,8 @@ static void soc_config_pwrmbase(void)
*
* Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16]
* to the value programmed in PMC PCI Offset 48h bit[31:16], this has an
- * implication of making sure the memory allocated to PWRMBASE to be 64KB
- * in size.
+ * implication of making sure the memory allocated to PWRMBASE to be
+ * 64KB in size.
*/
pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEA,
((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) |