diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2017-04-19 22:34:25 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-05-09 17:52:30 +0200 |
| commit | 502131a6ad3f3eae89ccd85402708ae90a6f2b4f (patch) | |
| tree | a5609dff3594e0a37c2007c08477072bbd48abc6 /src/soc/intel/skylake/bootblock | |
| parent | 709bc6eadab43d8faf96e1634dc439f2967c03f0 (diff) | |
soc/intel/skylake: Use intel/common/block/smbus code
Change-Id: I2ca32ab594552424e4f1358302641f159a3d7e62
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/smbus.c | 46 |
2 files changed, 4 insertions, 49 deletions
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index a92e4cffba..780c4aa235 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -22,6 +22,7 @@ #include <intelblocks/itss.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> +#include <intelblocks/smbus.h> #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/lpc.h> @@ -182,14 +183,14 @@ static void soc_config_tco(void) /* Disable TCO in SMBUS Device first before changing Base Address */ reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL); - reg32 &= ~SMBUS_TCO_EN; + reg32 &= ~TCO_EN; pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); /* Program TCO Base */ pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS); /* Enable TCO in SMBUS */ - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | SMBUS_TCO_EN); + pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN); /* * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] @@ -269,7 +270,7 @@ void pch_early_init(void) pch_enable_lpc(); /* Program SMBUS_BASE_ADDRESS and Enable it */ - enable_smbus(); + smbus_common_init(); /* Set up GPE configuration */ pmc_gpe_init(); diff --git a/src/soc/intel/skylake/bootblock/smbus.c b/src/soc/intel/skylake/bootblock/smbus.c deleted file mode 100644 index 14a9666176..0000000000 --- a/src/soc/intel/skylake/bootblock/smbus.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ids.h> -#include <device/pci_def.h> -#include <reg_script.h> -#include <soc/bootblock.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/smbus.h> - -static const struct reg_script smbus_init_script[] = { - /* Set SMBUS I/O base address */ - REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1), - /* Set SMBUS enable */ - REG_PCI_WRITE8(HOSTC, HST_EN), - /* Enable I/O access */ - REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), - /* Disable interrupts */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), - /* Clear errors */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), - /* Indicate the end of this array by REG_SCRIPT_END */ - REG_SCRIPT_END, -}; - -void enable_smbus(void) -{ - reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); -} |