soc/intel/skylake: Clean up UART code

Clean up and move UART related code under a single uart.c file.

Change-Id: I7ed03fc5fe79e38350d7edc70ad55d54db780fed
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

1 files changed, 0 insertions, 57 deletions

diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c
deleted file mode 100644
index f6e7e13b8e..0000000000
--- a/src/soc/intel/skylake/bootblock/uart.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- * Copyright (C) 2015 Intel Corporation
- * Copyright (C) 2016 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/uart.h>
-#include <device/pci_def.h>
-#include <gpio.h>
-#include <intelblocks/lpss.h>
-#include <intelblocks/pcr.h>
-#include <intelblocks/uart.h>
-#include <soc/bootblock.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-
-/* Serial IO UART controller legacy mode */
-#define PCR_SERIAL_IO_GPPRVRW7		0x618
-#define PCR_SIO_PCH_LEGACY_UART(idx)	(1 << (idx))
-
-/* UART2 pad configuration. Support RXD and TXD for now. */
-static const struct pad_config uart2_pads[] = {
-/* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-/* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
-};
-
-void pch_uart_init(void)
-{
-	uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
-
-	uart_common_init(PCH_DEV_UART2, base);
-
-	/* Put UART2 in byte access mode for 16550 compatibility */
-	if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {
-		pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
-			PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
-
-		/*
-		 * Dummy read after setting any of GPPRVRW7.
-		 * Required for UART 16550 8-bit Legacy mode to become active
-		 */
-		lpss_clk_read(base);
-	}
-
-	gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
-}