diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-08-10 13:57:07 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-16 23:29:56 +0000 |
| commit | b27aa82a50cde46d43ea0dd6ad797eb9c248e6c8 (patch) | |
| tree | 314c8bcf0ec0ce4c02997dabf9d3a98d94f87ed0 /src/soc/intel/skylake/bootblock | |
| parent | f710955b93dddb094b9dacf651fe8a0730b21500 (diff) | |
soc/intel/skylake: Add proper support to enable UART2 in 16550 mode
Need to perform a dummy read in order to activate LPSS UART's
16550 8-bit compatibility mode.
TEST=Able to get serial log in both 32 bit and 8 bit mode through
LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and
CONFIG_DRIVERS_UART_8250MEM selection.
Change-Id: I5f23fef4522743efd49167afb04d56032e16e417
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
| -rw-r--r-- | src/soc/intel/skylake/bootblock/uart.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c index b7ab241f77..f6e7e13b8e 100644 --- a/src/soc/intel/skylake/bootblock/uart.c +++ b/src/soc/intel/skylake/bootblock/uart.c @@ -27,9 +27,7 @@ /* Serial IO UART controller legacy mode */ #define PCR_SERIAL_IO_GPPRVRW7 0x618 -#define PCR_SIO_PCH_LEGACY_UART0 (1 << 0) -#define PCR_SIO_PCH_LEGACY_UART1 (1 << 1) -#define PCR_SIO_PCH_LEGACY_UART2 (1 << 2) +#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) /* UART2 pad configuration. Support RXD and TXD for now. */ static const struct pad_config uart2_pads[] = { @@ -44,9 +42,16 @@ void pch_uart_init(void) uart_common_init(PCH_DEV_UART2, base); /* Put UART2 in byte access mode for 16550 compatibility */ - if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) + if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) { pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART2); + PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); + + /* + * Dummy read after setting any of GPPRVRW7. + * Required for UART 16550 8-bit Legacy mode to become active + */ + lpss_clk_read(base); + } gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); } |