soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC

Use the Broadwell implementation as the comparison base for Skylake.

BRANCH=none
BUG=None
TEST=None

Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10340
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

5 files changed, 285 insertions, 0 deletions

diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc
new file mode 100644
index 0000000000..2ca5a4569f
--- /dev/null
+++ b/src/soc/intel/skylake/bootblock/Makefile.inc
@@ -0,0 +1 @@
+chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
new file mode 100644
index 0000000000..3a47d13f0a
--- /dev/null
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <arch/io.h>
+#include <halt.h>
+#include <cpu/intel/microcode/microcode.c>
+#include <soc/rcba.h>
+#include <soc/msr.h>
+
+static void set_var_mtrr(
+	unsigned reg, unsigned base, unsigned size, unsigned type)
+
+{
+	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+	msr_t basem, maskm;
+	basem.lo = base | type;
+	basem.hi = 0;
+	wrmsr(MTRRphysBase_MSR(reg), basem);
+	maskm.lo = ~(size - 1) | MTRRphysMaskValid;
+	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
+	wrmsr(MTRRphysMask_MSR(reg), maskm);
+}
+
+static void enable_rom_caching(void)
+{
+	msr_t msr;
+
+	disable_cache();
+	/* Why only top 4MiB ? */
+	set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
+	enable_cache();
+
+	/* Enable Variable MTRRs */
+	msr.hi = 0x00000000;
+	msr.lo = 0x00000800;
+	wrmsr(MTRRdefType_MSR, msr);
+}
+
+static void bootblock_mdelay(int ms)
+{
+	u32 target = ms * 24 * 1000;
+	msr_t current;
+	msr_t start = rdmsr(MSR_COUNTER_24_MHZ);
+
+	do {
+		current = rdmsr(MSR_COUNTER_24_MHZ);
+	} while ((current.lo - start.lo) < target);
+}
+
+static void set_flex_ratio_to_tdp_nominal(void)
+{
+	msr_t flex_ratio, msr;
+	u32 soft_reset;
+	u8 nominal_ratio;
+
+	/* Check for Flex Ratio support */
+	flex_ratio = rdmsr(MSR_FLEX_RATIO);
+	if (!(flex_ratio.lo & FLEX_RATIO_EN))
+		return;
+
+	/* Check for >0 configurable TDPs */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if (((msr.hi >> 1) & 3) == 0)
+		return;
+
+	/* Use nominal TDP ratio for flex ratio */
+	msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+	nominal_ratio = msr.lo & 0xff;
+
+	/* See if flex ratio is already set to nominal TDP ratio */
+	if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
+		return;
+
+	/* Set flex ratio to nominal TDP ratio */
+	flex_ratio.lo &= ~0xff00;
+	flex_ratio.lo |= nominal_ratio << 8;
+	flex_ratio.lo |= FLEX_RATIO_LOCK;
+	wrmsr(MSR_FLEX_RATIO, flex_ratio);
+
+	/* Set flex ratio in soft reset data register bits 11:6.
+	 * RCBA region is enabled in southbridge bootblock */
+	soft_reset = RCBA32(SOFT_RESET_DATA);
+	soft_reset &= ~(0x3f << 6);
+	soft_reset |= (nominal_ratio & 0x3f) << 6;
+	RCBA32(SOFT_RESET_DATA) = soft_reset;
+
+	/* Set soft reset control to use register value */
+	RCBA32_OR(SOFT_RESET_CTRL, 1);
+
+	/* Delay before reset to avoid potential TPM lockout */
+	bootblock_mdelay(30);
+
+	/* Issue warm reset, will be "CPU only" due to soft reset data */
+	outb(0x0, 0xcf9);
+	outb(0x6, 0xcf9);
+	halt();
+}
+
+static void check_for_clean_reset(void)
+{
+	msr_t msr;
+	msr = rdmsr(MTRRdefType_MSR);
+
+	/* Use the MTRR default type MSR as a proxy for detecting INIT#.
+	 * Reset the system if any known bits are set in that MSR. That is
+	 * an indication of the CPU not being properly reset. */
+	if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) {
+		outb(0x0, 0xcf9);
+		outb(0x6, 0xcf9);
+		halt();
+	}
+}
+
+static void bootblock_cpu_init(void)
+{
+	/* Set flex ratio and reset if needed */
+	set_flex_ratio_to_tdp_nominal();
+	check_for_clean_reset();
+	enable_rom_caching();
+	intel_update_microcode_from_cbfs();
+}
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
new file mode 100644
index 0000000000..2fa722097c
--- /dev/null
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/rcba.h>
+#include <soc/spi.h>
+
+/*
+ * Enable Prefetching and Caching.
+ */
+static void enable_spi_prefetch(void)
+{
+	u8 reg8 = pci_read_config8(PCH_DEV_LPC, 0xdc);
+	reg8 &= ~(3 << 2);
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	pci_write_config8(PCH_DEV_LPC, 0xdc, reg8);
+}
+
+
+static void map_rcba(void)
+{
+	pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1);
+}
+
+static void enable_port80_on_lpc(void)
+{
+	/* Enable port 80 POST on LPC. The chipset does this by default,
+	 * but it doesn't appear to hurt anything. */
+	u32 gcs = RCBA32(GCS);
+	gcs = gcs & ~0x4;
+	RCBA32(GCS) = gcs;
+}
+
+static void set_spi_speed(void)
+{
+	u32 fdod;
+	u8 ssfc;
+
+	/* Observe SPI Descriptor Component Section 0 */
+	SPIBAR32(SPIBAR_FDOC) = 0x1000;
+
+	/* Extract the Write/Erase SPI Frequency from descriptor */
+	fdod = SPIBAR32(SPIBAR_FDOD);
+	fdod >>= 24;
+	fdod &= 7;
+
+	/* Set Software Sequence frequency to match */
+	ssfc = SPIBAR8(SPIBAR_SSFC + 2);
+	ssfc &= ~7;
+	ssfc |= fdod;
+	SPIBAR8(SPIBAR_SSFC + 2) = ssfc;
+}
+
+static void bootblock_southbridge_init(void)
+{
+	map_rcba();
+	enable_spi_prefetch();
+	enable_port80_on_lpc();
+	set_spi_speed();
+}
diff --git a/src/soc/intel/skylake/bootblock/systemagent.c b/src/soc/intel/skylake/bootblock/systemagent.c
new file mode 100644
index 0000000000..15e7fc88b4
--- /dev/null
+++ b/src/soc/intel/skylake/bootblock/systemagent.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <soc/pci_devs.h>
+#include <soc/systemagent.h>
+
+static void bootblock_northbridge_init(void)
+{
+	uint32_t reg;
+
+	/*
+	 * The "io" variant of the config access is explicitly used to
+	 * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+	 * to true. That way all subsequent non-explicit config accesses use
+	 * MCFG. This code also assumes that bootblock_northbridge_init() is
+	 * the first thing called in the non-asm boot block code. The final
+	 * assumption is that no assembly code is using the
+	 * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config accesses.
+	 *
+	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
+	 * 4GiB.
+	 */
+	reg = 0;
+	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
+	reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
+	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
+}
diff --git a/src/soc/intel/skylake/bootblock/timestamp.inc b/src/soc/intel/skylake/bootblock/timestamp.inc
new file mode 100644
index 0000000000..f565775ed8
--- /dev/null
+++ b/src/soc/intel/skylake/bootblock/timestamp.inc
@@ -0,0 +1,19 @@
+/* Store the initial timestamp for booting in mmx registers. This works
+ * because the bootblock isn't being compiled with MMX support so mm0 and
+ * mm1 will be preserved into romstage. */
+	.code32
+
+.global stash_timestamp
+stash_timestamp:
+
+	/* Save the BIST value */
+	movl	%eax, %ebp
+
+	finit
+	rdtsc
+	movd	%eax, %mm0
+	movd	%edx, %mm1
+
+	/* Restore the BIST value to %eax */
+	movl	%ebp, %eax
+