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author | Chris Zhou <chris_zhou@compal.corp-partner.google.com> | 2018-10-08 11:36:48 +0800 |
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committer | Martin Roth <martinroth@google.com> | 2018-10-09 14:33:22 +0000 |
commit | 3087bf528352d1ee663e028cd951c94199b6c322 (patch) | |
tree | 1d95cda0b4323eb1daee0ffb92260a0a92e8a472 /src/soc/intel/skylake/bootblock | |
parent | 56dceb2e1a05191d6bf10498a461673f9a6c5279 (diff) |
mb/google/kahlee/variants/liara: Update H1/TP/TS i2c timings
After adjustment on Liara EVT
H1: 392.03 KHz
TP: 397.87 KHz
TS: 397.71 KHz
BUG=b:116309237
BRANCH=master
TEST=emerge-grunt coreboot chromeos-bootimage
measure by scope
Change-Id: Ib5d7ce09ac58f33ee826d7541e1a0d14a03add9a
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
0 files changed, 0 insertions, 0 deletions