diff options
author | Subrata Banik <subrata.banik@intel.com> | 2016-07-24 00:36:12 +0530 |
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committer | Andrey Petrov <andrey.petrov@intel.com> | 2016-07-28 05:15:58 +0200 |
commit | e4a8537ce20d801a5985ba6268ae83593063a4bf (patch) | |
tree | efdc7dcf51a9b91f8d4f6f8db9c8a0ef951ca62d /src/soc/intel/skylake/bootblock/uart.c | |
parent | 68d5d8b28ab399b8dfb8ef6477d25311a319f2d5 (diff) |
soc/intel/skylake: Add C entry bootblock support
List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34
Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/bootblock/uart.c')
-rw-r--r-- | src/soc/intel/skylake/bootblock/uart.c | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c new file mode 100644 index 0000000000..ff1687c520 --- /dev/null +++ b/src/soc/intel/skylake/bootblock/uart.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/uart.h> +#include <device/pci_def.h> +#include <stdint.h> +#include <soc/bootblock.h> +#include <soc/pci_devs.h> +#include <soc/pcr.h> +#include <soc/serialio.h> +#include <gpio.h> + +/* UART2 pad configuration. Support RXD and TXD for now. */ +static const struct pad_config uart2_pads[] = { +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +}; + +void pch_uart_init(void) +{ + device_t dev = PCH_DEV_UART2; + u32 tmp; + u8 *base = (void *)uart_platform_base(CONFIG_UART_FOR_CONSOLE); + + /* Set configured UART2 base address */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base); + + /* Enable memory access and bus master */ + tmp = pci_read_config32(dev, PCI_COMMAND); + tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, tmp); + + /* Take UART2 out of reset */ + tmp = read32(base + SIO_REG_PPR_RESETS); + tmp |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB | + SIO_REG_PPR_RESETS_IDMA; + write32(base + SIO_REG_PPR_RESETS, tmp); + + /* + * Set M and N divisor inputs and enable clock. + * Main reference frequency to UART is: + * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz + */ + tmp = read32(base + SIO_REG_PPR_CLOCK); + tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE | + (SIO_REG_PPR_CLOCK_N_DIV << 16) | + (SIO_REG_PPR_CLOCK_M_DIV << 1); + write32(base + SIO_REG_PPR_CLOCK, tmp); + + /* Put UART2 in byte access mode for 16550 compatibility */ + if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) + pcr_andthenor32(PID_SERIALIO, + R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2); + + gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} |