diff options
author | Naresh G Solanki <naresh.solanki@intel.com> | 2016-08-11 14:56:28 +0530 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-08-18 18:13:42 +0200 |
commit | ecd9a94213216f2f50e501e6b27ee390928e0dbf (patch) | |
tree | 33e48614fb462ccadb76e17950d6a8b49ee35dd5 /src/soc/intel/skylake/bootblock/cpu.c | |
parent | cf73c1317dd1ab62a96eb17ed6d9c8590fb4c514 (diff) |
soc/intel/skylake: Move bootblock specific code from skylake/romstage
There is a lot of code that is being referred to in bootblock but
resides under skylake/romstage folder. Hence move this code
into skylake/bootblock, and update the relevant header files
and Makefiles.
TEST=Build and Boot kunimitsu.
Change-Id: If94e16fe54ccb7ced9c6b480a661609bdd2dfa41
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16225
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/bootblock/cpu.c')
-rw-r--r-- | src/soc/intel/skylake/bootblock/cpu.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 8c1e58a65f..3cea8bdcfc 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -17,9 +17,11 @@ #include <stdint.h> #include <delay.h> #include <arch/io.h> +#include <console/console.h> #include <cpu/intel/microcode/microcode.c> #include <reset.h> #include <soc/bootblock.h> +#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -105,3 +107,27 @@ void bootblock_cpu_init(void) set_flex_ratio_to_tdp_nominal(); intel_update_microcode_from_cbfs(); } + +void set_max_freq(void) +{ + msr_t msr, perf_ctl, platform_info; + + /* Check for configurable TDP option */ + platform_info = rdmsr(MSR_PLATFORM_INFO); + + if ((platform_info.hi >> 1) & 3) { + /* Set to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else { + /* Platform Info bits 15:8 give max ratio */ + msr = rdmsr(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; + } + + perf_ctl.hi = 0; + wrmsr(IA32_PERF_CTL, perf_ctl); + + printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", + ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); +} |