soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC

Use the Broadwell implementation as the comparison base for Skylake.

BRANCH=none
BUG=None
TEST=None

Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10340
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

21 files changed, 3543 insertions, 0 deletions

diff --git a/src/soc/intel/skylake/acpi/adsp.asl b/src/soc/intel/skylake/acpi/adsp.asl
new file mode 100644
index 0000000000..cb10d9a9ad
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/adsp.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device (ADSP)
+{
+	Method (_HID, 0, Serialized)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3438")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C8")
+	}
+	Name (_UID, 1)
+	Name (_DDN, "Intel Smart Sound Technology")
+
+	Name (RBUF, ResourceTemplate ()
+	{
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00100000, BAR0)
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR1)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {3}
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		// Update BAR address and length if set in NVS
+		If (LNotEqual (\S8B0, Zero)) {
+			CreateDwordField (^RBUF, ^BAR0._BAS, B8A0)
+			CreateDwordField (^RBUF, ^BAR1._BAS, B8A1)
+			Store (\S8B0, B8A0)
+			Store (\S8B1, B8A1)
+		}
+
+		Return (RBUF)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		If (LEqual (\S8EN, 0)) {
+			Return (0x0)
+		} Else {
+			Return (0xF)
+		}
+	}
+
+	Device (I2S0)
+	{
+		Name (_ADR, 0)
+	}
+
+	Device (I2S1)
+	{
+		Name (_ADR, 1)
+	}
+}
diff --git a/src/soc/intel/skylake/acpi/cpu.asl b/src/soc/intel/skylake/acpi/cpu.asl
new file mode 100644
index 0000000000..2921ceae5e
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/cpu.asl
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* These devices are created at runtime */
+External (\_PR.CP00, DeviceObj)
+External (\_PR.CP01, DeviceObj)
+External (\_PR.CP02, DeviceObj)
+External (\_PR.CP03, DeviceObj)
+External (\_PR.CP04, DeviceObj)
+External (\_PR.CP05, DeviceObj)
+External (\_PR.CP06, DeviceObj)
+External (\_PR.CP07, DeviceObj)
+
+/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
+Method (PNOT)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (\_PR.CP00, 0x81)  // _CST
+		Notify (\_PR.CP01, 0x81)  // _CST
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (\_PR.CP02, 0x81)  // _CST
+		Notify (\_PR.CP03, 0x81)  // _CST
+	}
+	If (LGreaterEqual (\PCNT, 8)) {
+		Notify (\_PR.CP04, 0x81)  // _CST
+		Notify (\_PR.CP05, 0x81)  // _CST
+		Notify (\_PR.CP06, 0x81)  // _CST
+		Notify (\_PR.CP07, 0x81)  // _CST
+	}
+}
+
+/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
+Method (PPCN)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (\_PR.CP00, 0x80)  // _PPC
+		Notify (\_PR.CP01, 0x80)  // _PPC
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (\_PR.CP02, 0x80)  // _PPC
+		Notify (\_PR.CP03, 0x80)  // _PPC
+	}
+	If (LGreaterEqual (\PCNT, 8)) {
+		Notify (\_PR.CP04, 0x80)  // _PPC
+		Notify (\_PR.CP05, 0x80)  // _PPC
+		Notify (\_PR.CP06, 0x80)  // _PPC
+		Notify (\_PR.CP07, 0x80)  // _PPC
+	}
+}
+
+/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
+Method (TNOT)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (\_PR.CP00, 0x82)  // _TPC
+		Notify (\_PR.CP01, 0x82)  // _TPC
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (\_PR.CP02, 0x82)  // _TPC
+		Notify (\_PR.CP03, 0x82)  // _TPC
+	}
+	If (LGreaterEqual (\PCNT, 8)) {
+		Notify (\_PR.CP04, 0x82)  // _TPC
+		Notify (\_PR.CP05, 0x82)  // _TPC
+		Notify (\_PR.CP06, 0x82)  // _TPC
+		Notify (\_PR.CP07, 0x82)  // _TPC
+	}
+}
+
+/* Return a package containing enabled processor entries */
+Method (PPKG)
+{
+	If (LGreaterEqual (\PCNT, 8)) {
+		Return (Package()
+		{
+			\_PR.CP00,
+			\_PR.CP01,
+			\_PR.CP02,
+			\_PR.CP03,
+			\_PR.CP04,
+			\_PR.CP05,
+			\_PR.CP06,
+			\_PR.CP07
+		})
+	} ElseIf (LGreaterEqual (\PCNT, 4)) {
+		Return (Package ()
+		{
+			\_PR.CP00,
+			\_PR.CP01,
+			\_PR.CP02,
+			\_PR.CP03
+		})
+	} ElseIf (LGreaterEqual (\PCNT, 2)) {
+		Return (Package ()
+		{
+			\_PR.CP00,
+			\_PR.CP01
+		})
+	} Else {
+		Return (Package ()
+		{
+			\_PR.CP00
+		})
+	}
+}
diff --git a/src/soc/intel/skylake/acpi/ctdp.asl b/src/soc/intel/skylake/acpi/ctdp.asl
new file mode 100644
index 0000000000..a2a8fb4d2c
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/ctdp.asl
@@ -0,0 +1,237 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Scope (\_SB.PCI0.MCHC)
+{
+	Mutex (CTCM, 1)		/* CTDP Switch Mutex (sync level 1) */
+	Name (CTCC, 0)		/* CTDP Current Selection */
+	Name (CTCN, 0)		/* CTDP Nominal Select */
+	Name (CTCD, 1)		/* CTDP Down Select */
+	Name (CTCU, 2)		/* CTDP Up Select */
+	Name (SPL1, 0)		/* Saved PL1 value */
+
+	OperationRegion (MCHB, SystemMemory,
+			Add (MCH_BASE_ADDRESS, 0x5000), 0x1000)
+	Field (MCHB, DWordAcc, Lock, Preserve)
+	{
+		Offset (0x930), /* PACKAGE_POWER_SKU */
+		CTDN, 15,	/* CTDP Nominal PL1 */
+		Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */
+		PUNI, 4,	/* Power Units */
+		,     4,
+		EUNI, 5,	/* Energy Units */
+		,     3,
+		TUNI, 4,	/* Time Units */
+		Offset (0x958), /* PLATFORM_INFO */
+		,     40,
+		LFM_, 8,	/* Maximum Efficiency Ratio (LFM) */
+		Offset (0x9a0), /* TURBO_POWER_LIMIT1 */
+		PL1V, 15,	/* Power Limit 1 Value */
+		PL1E, 1,	/* Power Limit 1 Enable */
+		PL1C, 1,	/* Power Limit 1 Clamp */
+		PL1T, 7,	/* Power Limit 1 Time */
+		Offset (0x9a4), /* TURBO_POWER_LIMIT2 */
+		PL2V, 15,	/* Power Limit 2 Value */
+		PL2E, 1,	/* Power Limit 2 Enable */
+		PL2C, 1,	/* Power Limit 2 Clamp */
+		PL2T, 7,	/* Power Limit 2 Time */
+		Offset (0xf3c), /* CONFIG_TDP_NOMINAL */
+		TARN, 8,	/* CTDP Nominal Turbo Activation Ratio */
+		Offset (0xf40), /* CONFIG_TDP_LEVEL1 */
+		CTDD, 15,	/* CTDP Down PL1 */
+		,     1,
+		TARD, 8,	/* CTDP Down Turbo Activation Ratio */
+		Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */
+		CTDU, 15,	/* CTDP Up PL1 */
+		,     1,
+		TARU, 8,	/* CTDP Up Turbo Activation Ratio */
+		Offset (0xf50), /* CONFIG_TDP_CONTROL */
+		CTCS, 2,	/* CTDP Select */
+		Offset (0xf54), /* TURBO_ACTIVATION_RATIO */
+		TARS, 8,	/* Turbo Activation Ratio Select */
+	}
+
+	/*
+	 * Search CPU0 _PSS looking for control=arg0 and then
+	 * return previous P-state entry number for new _PPC
+	 *
+	 * Format of _PSS:
+	 *   Name (_PSS, Package () {
+	 *     Package (6) { freq, power, tlat, blat, control, status }
+	 *   }
+	 */
+	External (\_PR.CP00._PSS)
+	Method (PSSS, 1, NotSerialized)
+	{
+		Store (One, Local0) /* Start at P1 */
+		Store (SizeOf (\_PR.CP00._PSS), Local1)
+
+		While (LLess (Local0, Local1)) {
+			/* Store _PSS entry Control value to Local2 */
+			ShiftRight (DeRefOf (Index (DeRefOf (Index
+			      (\_PR.CP00._PSS, Local0)), 4)), 8, Local2)
+			If (LEqual (Local2, Arg0)) {
+				Return (Subtract (Local0, 1))
+			}
+			Increment (Local0)
+		}
+
+		Return (0)
+	}
+
+	/* Calculate PL2 based on chip type */
+	Method (CPL2, 1, NotSerialized)
+	{
+		/* Haswell ULT PL2 = 25W */
+		/* FIXME: update for broadwell */
+		Return (Multiply (25, 8))
+	}
+
+	/* Set Config TDP Down */
+	Method (STND, 0, Serialized)
+	{
+		If (Acquire (CTCM, 100)) {
+			Return (0)
+		}
+		If (LEqual (CTCD, CTCC)) {
+			Release (CTCM)
+			Return (0)
+		}
+
+		Store ("Set TDP Down", Debug)
+
+		/* Set CTC */
+		Store (CTCD, CTCS)
+
+		/* Set TAR */
+		Store (TARD, TARS)
+
+		/* Set PPC limit and notify OS */
+		Store (PSSS (TARD), PPCM)
+		PPCN ()
+
+		/* Set PL2 */
+		Store (CPL2 (CTDD), PL2V)
+
+		/* Set PL1 */
+		Store (CTDD, PL1V)
+
+		/* Store the new TDP Down setting */
+		Store (CTCD, CTCC)
+
+		Release (CTCM)
+		Return (1)
+	}
+
+	/* Set Config TDP Nominal from Down */
+	Method (STDN, 0, Serialized)
+	{
+		If (Acquire (CTCM, 100)) {
+			Return (0)
+		}
+		If (LEqual (CTCN, CTCC)) {
+			Release (CTCM)
+			Return (0)
+		}
+
+		Store ("Set TDP Nominal", Debug)
+
+		/* Set PL1 */
+		Store (CTDN, PL1V)
+
+		/* Set PL2 */
+		Store (CPL2 (CTDN), PL2V)
+
+		/* Set PPC limit and notify OS */
+		Store (PSSS (TARN), PPCM)
+		PPCN ()
+
+		/* Set TAR */
+		Store (TARN, TARS)
+
+		/* Set CTC */
+		Store (CTCN, CTCS)
+
+		/* Store the new TDP Nominal setting */
+		Store (CTCN, CTCC)
+
+		Release (CTCM)
+		Return (1)
+	}
+
+	/* Calculate PL1 value based on requested TDP */
+	Method (TDPP, 1, NotSerialized)
+	{
+		Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0))
+	}
+
+	/* Enable Controllable TDP to limit PL1 to requested value */
+	Method (CTLE, 1, Serialized)
+	{
+		If (Acquire (CTCM, 100)) {
+			Return (0)
+		}
+
+		Store ("Enable PL1 Limit", Debug)
+
+		/* Set _PPC to LFM */
+		Store (PSSS (LFM_), Local0)
+		Add (Local0, 1, PPCM)
+		\PPCN ()
+
+		/* Set TAR to LFM-1 */
+		Subtract (LFM_, 1, TARS)
+
+		/* Set PL1 to desired value */
+		Store (PL1V, SPL1)
+		Store (TDPP (Arg0), PL1V)
+
+		/* Set PL1 CLAMP bit */
+		Store (One, PL1C)
+
+		Release (CTCM)
+		Return (1)
+	}
+
+	/* Disable Controllable TDP */
+	Method (CTLD, 0, Serialized)
+	{
+		If (Acquire (CTCM, 100)) {
+			Return (0)
+		}
+
+		Store ("Disable PL1 Limit", Debug)
+
+		/* Clear PL1 CLAMP bit */
+		Store (Zero, PL1C)
+
+		/* Set PL1 to normal value */
+		Store (SPL1, PL1V)
+
+		/* Set TAR to 0 */
+		Store (Zero, TARS)
+
+		/* Set _PPC to 0 */
+		Store (Zero, PPCM)
+		\PPCN ()
+
+		Release (CTCM)
+		Return (1)
+	}
+}
diff --git a/src/soc/intel/skylake/acpi/device_nvs.asl b/src/soc/intel/skylake/acpi/device_nvs.asl
new file mode 100644
index 0000000000..1d2aa78edb
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/device_nvs.asl
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Device Enabled in ACPI Mode */
+
+S0EN,	8,	// DMA Enable
+S1EN,	8,	// I2C0 Enable
+S2EN,	8,	// I2C1 Enable
+S3EN,	8,	// SPI0 Enable
+S4EN,	8,	// SPI1 Enable
+S5EN,	8,	// UART0 Enable
+S6EN,	8,	// UART1 Enable
+S7EN,	8,	// SDIO Enable
+S8EN,	8,	// ADSP Enable
+
+/* BAR 0 */
+
+S0B0,	32,	// DMA BAR0
+S1B0,	32,	// I2C0 BAR0
+S2B0,	32,	// I2C1 BAR0
+S3B0,	32,	// SPI0 BAR0
+S4B0,	32,	// SPI1 BAR0
+S5B0,	32,	// UART0 BAR0
+S6B0,	32,	// UART1 BAR0
+S7B0,	32,	// SDIO BAR0
+S8B0,	32,	// ADSP BAR0
+
+/* BAR 1 */
+
+S0B1,	32,	// DMA BAR1
+S1B1,	32,	// I2C0 BAR1
+S2B1,	32,	// I2C1 BAR1
+S3B1,	32,	// SPI0 BAR1
+S4B1,	32,	// SPI1 BAR1
+S5B1,	32,	// UART0 BAR1
+S6B1,	32,	// UART1 BAR1
+S7B1,	32,	// SDIO BAR1
+S8B1,	32,	// ADSP BAR1
diff --git a/src/soc/intel/skylake/acpi/ehci.asl b/src/soc/intel/skylake/acpi/ehci.asl
new file mode 100644
index 0000000000..a2e704fccf
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/ehci.asl
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// EHCI Controller 0:1d.0
+
+Device (EHCI)
+{
+	Name(_ADR, 0x001d0000)
+	Name (_PRW, Package(){ 0x6d, 3 })
+
+	// Leave USB ports on for to allow Wake from USB
+
+	Method(_S3D,0)	// Highest D State in S3 State
+	{
+		Return (2)
+	}
+
+	Method(_S4D,0)	// Highest D State in S4 State
+	{
+		Return (2)
+	}
+
+	Device (HUB7)
+	{
+		Name (_ADR, 0x00000000)
+
+		// How many are there?
+		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
+		Device (PRT2) { Name (_ADR, 2) } // USB Port 1
+		Device (PRT3) { Name (_ADR, 3) } // USB Port 2
+		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
+		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
+		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+	}
+}
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
new file mode 100644
index 0000000000..223d21a676
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Global Variables */
+
+Name (\PICM, 0)		// IOAPIC/8259
+
+/*
+ * Global ACPI memory region. This region is used for passing information
+ * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
+ * Since we don't know where this will end up in memory at ACPI compile time,
+ * we have to fix it up in coreboot's ACPI creation phase.
+ */
+
+External(NVSA)
+OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+	/* Miscellaneous */
+	Offset (0x00),
+	OSYS,	16,	// 0x00 - Operating System
+	SMIF,	8,	// 0x02 - SMI function
+	PRM0,	8,	// 0x03 - SMI function parameter
+	PRM1,	8,	// 0x04 - SMI function parameter
+	SCIF,	8,	// 0x05 - SCI function
+	PRM2,	8,	// 0x06 - SCI function parameter
+	PRM3,	8,	// 0x07 - SCI function parameter
+	LCKF,	8,	// 0x08 - Global Lock function for EC
+	PRM4,	8,	// 0x09 - Lock function parameter
+	PRM5,	8,	// 0x0a - Lock function parameter
+	PCNT,	8,	// 0x0b - Processor Count
+	PPCM,	8,	// 0x0c - Max PPC State
+	TMPS,	8,	// 0x0d - Temperature Sensor ID
+	TLVL,	8,	// 0x0e - Throttle Level Limit
+	FLVL,	8,	// 0x0f - Current FAN Level
+	TCRT,	8,	// 0x10 - Critical Threshold
+	TPSV,	8,	// 0x11 - Passive Threshold
+	TMAX,	8,	// 0x12 - CPU Tj_max
+	S5U0,	8,	// 0x13 - Enable USB in S5
+	S3U0,	8,	// 0x14 - Enable USB in S3
+	S33G,	8,	// 0x15 - Enable 3G in S3
+	LIDS,	8,	// 0x16 - LID State
+	PWRS,	8,	// 0x17 - AC Power State
+	CMEM,	32,	// 0x18 - 0x1b - CBMEM TOC
+	CBMC,	32,	// 0x1c - 0x1f - Coreboot Memory Console
+	PM1I,	64,	// 0x20 - 0x27 - PM1 wake status bit
+	GPEI,	64,	// 0x28 - 0x2f - GPE wake status bit
+
+	/* ChromeOS specific */
+	Offset (0x100),
+	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
+
+	/* Device specific */
+	Offset (0x1000),
+	#include "device_nvs.asl"
+}
+
+/* Set flag to enable USB charging in S3 */
+Method (S3UE)
+{
+	Store (One, \S3U0)
+}
+
+/* Set flag to disable USB charging in S3 */
+Method (S3UD)
+{
+	Store (Zero, \S3U0)
+}
+
+/* Set flag to enable USB charging in S5 */
+Method (S5UE)
+{
+	Store (One, \S5U0)
+}
+
+/* Set flag to disable USB charging in S5 */
+Method (S5UD)
+{
+	Store (Zero, \S5U0)
+}
+
+/* Set flag to enable 3G module in S3 */
+Method (S3GE)
+{
+	Store (One, \S33G)
+}
+
+/* Set flag to disable 3G module in S3 */
+Method (S3GD)
+{
+	Store (Zero, \S33G)
+}
diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl
new file mode 100644
index 0000000000..c6d8753975
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/gpio.asl
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device (GPIO)
+{
+	// GPIO Controller
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3437")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C7")
+	}
+	Name (_UID, 1)
+
+	Name (RBUF, ResourceTemplate()
+	{
+		DWordIo (ResourceProducer,
+			MinFixed,    // IsMinFixed
+			MaxFixed,    // IsMaxFixed
+			PosDecode,   // Decode
+			EntireRange, // ISARanges
+			0x00000000,  // AddressGranularity
+			0x00000000,  // AddressMinimum
+			0x00000000,  // AddressMaximum
+			0x00000000,  // AddressTranslation
+			0x00000000,  // RangeLength
+			,            // ResourceSourceIndex
+			,            // ResourceSource
+			BAR0)
+		// Disabled due to IRQ storm: http://crosbug.com/p/29548
+		//Interrupt (ResourceConsumer,
+		//	Level, ActiveHigh, Shared, , , ) {14}
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		CreateDwordField (^RBUF, ^BAR0._MIN, BMIN)
+		CreateDwordField (^RBUF, ^BAR0._MAX, BMAX)
+		CreateDwordField (^RBUF, ^BAR0._LEN, BLEN)
+
+		Store (GPIO_BASE_SIZE, BLEN)
+		Store (GPIO_BASE_ADDRESS, BMIN)
+		Store (Subtract (Add (GPIO_BASE_ADDRESS,
+				      GPIO_BASE_SIZE), 1), BMAX)
+
+		Return (RBUF)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0xF)
+	}
+
+	// GWAK: Setup GPIO as ACPI GPE for Wake
+	// Arg0: GPIO Number
+	Method (GWAK, 1, NotSerialized)
+	{
+		// Local0 = GPIO Base Address
+		Store (And (GPBS, Not(0x1)), Local0)
+
+		// Local1 = BANK, Local2 = OFFSET
+		Divide (Arg0, 32, Local2, Local1)
+
+		//
+		// Set OWNER to ACPI
+		//
+
+		// Local3 = GPIOBASE + GPIO_OWN(BANK)
+		Store (Add (Local0, Multiply (Local1, 0x4)), Local3)
+
+		// GPIO_OWN(BANK)
+		OperationRegion (IOWN, SystemIO, Local3, 4)
+		Field (IOWN, AnyAcc, NoLock, Preserve) {
+			GOWN, 32,
+		}
+
+		// GPIO_OWN[GPIO] = 0 (ACPI)
+		Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN)
+
+		//
+		// Set ROUTE to SCI
+		//
+
+		// Local3 = GPIOBASE + GPIO_ROUTE(BANK)
+		Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3)
+
+		// GPIO_ROUTE(BANK)
+		OperationRegion (IROU, SystemIO, Local3, 4)
+		Field (IROU, AnyAcc, NoLock, Preserve) {
+			GROU, 32,
+		}
+
+		// GPIO_ROUTE[GPIO] = 0 (SCI)
+		Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU)
+
+		//
+		// Set GPnCONFIG to GPIO|INPUT|INVERT
+		//
+
+		// Local3 = GPIOBASE + GPnCONFIG0(GPIO)
+		Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3)
+
+		// GPnCONFIG(GPIO)
+		OperationRegion (GPNC, SystemIO, Local3, 8)
+		Field (GPNC, AnyAcc, NoLock, Preserve) {
+			GMOD, 1,  // MODE:   0=NATIVE 1=GPIO
+			, 1,
+			GIOS, 1,  // IO_SEL: 0=OUTPUT 1=INPUT
+			GINV, 1,  // INVERT: 0=NORMAL 1=INVERT
+			GLES, 1,  // LxEB:   0=EDGE 1=LEVEL
+			, 24,
+			ILVL, 1,  // INPUT:  0=LOW 1=HIGH
+			OLVL, 1,  // OUTPUT: 0=LOW 1=HIGH
+			GPWP, 2,  // PULLUP: 00=NONE 01=DOWN 10=UP 11=INVALID
+			ISEN, 1,  // SENSE:  0=ENABLE 1=DISABLE
+		}
+
+		Store (0x1, GMOD) // GPIO
+		Store (0x1, GIOS) // INPUT
+		Store (0x1, GINV) // INVERT
+	}
+}
diff --git a/src/soc/intel/skylake/acpi/hda.asl b/src/soc/intel/skylake/acpi/hda.asl
new file mode 100644
index 0000000000..21736615ac
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/hda.asl
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Intel PCH HDA */
+
+// Intel High Definition Audio (Azalia) 0:1b.0
+
+Device (HDEF)
+{
+	Name (_ADR, 0x001b0000)
+	Name (_PRW, Package () { 0x6d, 3 })
+}
diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl
new file mode 100644
index 0000000000..ba550e2a46
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/irqlinks.asl
@@ -0,0 +1,492 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device (LNKA)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 1)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTA)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ (Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLA, ResourceTemplate()
+		{
+			IRQ (Level, ActiveLow, Shared) {}
+		})
+		CreateWordField (RTLA, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTA
+		ShiftLeft (1, And (PRTA, 0x0f), IRQ0)
+
+		Return (RTLA)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField (Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit (IRQ0, Local0)
+
+		Decrement(Local0)
+		Store (Local0, PRTA)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And (PRTA, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKB)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 2)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTB)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ (Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLB, ResourceTemplate()
+		{
+			IRQ (Level, ActiveLow, Shared) {}
+		})
+		CreateWordField (RTLB, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTB
+		ShiftLeft (1, And (PRTB, 0x0f), IRQ0)
+
+		Return (RTLB)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField (Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit (IRQ0, Local0)
+
+		Decrement(Local0)
+		Store (Local0, PRTB)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And (PRTB, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKC)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 3)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTC)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ (Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLC, ResourceTemplate()
+		{
+			IRQ (Level, ActiveLow, Shared) {}
+		})
+		CreateWordField (RTLC, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTC
+		ShiftLeft (1, And (PRTC, 0x0f), IRQ0)
+
+		Return (RTLC)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField (Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit (IRQ0, Local0)
+
+		Decrement(Local0)
+		Store (Local0, PRTC)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And (PRTC, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKD)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 4)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTD)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ (Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLD, ResourceTemplate()
+		{
+			IRQ (Level, ActiveLow, Shared) {}
+		})
+		CreateWordField (RTLD, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTD
+		ShiftLeft (1, And (PRTD, 0x0f), IRQ0)
+
+		Return (RTLD)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField (Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit (IRQ0, Local0)
+
+		Decrement(Local0)
+		Store (Local0, PRTD)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And (PRTD, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKE)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 5)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTE)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ (Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLE, ResourceTemplate()
+		{
+			IRQ (Level, ActiveLow, Shared) {}
+		})
+		CreateWordField (RTLE, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTE
+		ShiftLeft (1, And (PRTE, 0x0f), IRQ0)
+
+		Return (RTLE)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField (Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit (IRQ0, Local0)
+
+		Decrement(Local0)
+		Store (Local0, PRTE)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And (PRTE, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKF)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 6)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTF)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ (Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLF, ResourceTemplate()
+		{
+			IRQ (Level, ActiveLow, Shared) {}
+		})
+		CreateWordField (RTLF, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTF
+		ShiftLeft (1, And (PRTF, 0x0f), IRQ0)
+
+		Return (RTLF)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField (Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit (IRQ0, Local0)
+
+		Decrement(Local0)
+		Store (Local0, PRTF)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And (PRTF, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKG)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 7)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTG)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ (Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLG, ResourceTemplate()
+		{
+			IRQ (Level, ActiveLow, Shared) {}
+		})
+		CreateWordField (RTLG, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTG
+		ShiftLeft (1, And (PRTG, 0x0f), IRQ0)
+
+		Return (RTLG)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField (Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit (IRQ0, Local0)
+
+		Decrement(Local0)
+		Store (Local0, PRTG)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And (PRTG, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKH)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 8)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTH)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ (Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLH, ResourceTemplate()
+		{
+			IRQ (Level, ActiveLow, Shared) {}
+		})
+		CreateWordField (RTLH, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTH
+		ShiftLeft (1, And (PRTH, 0x0f), IRQ0)
+
+		Return (RTLH)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField (Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit (IRQ0, Local0)
+
+		Decrement(Local0)
+		Store (Local0, PRTH)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And (PRTH, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl
new file mode 100644
index 0000000000..2b574f756d
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/lpc.asl
@@ -0,0 +1,208 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Intel LPC Bus Device  - 0:1f.0
+
+Device (LPCB)
+{
+	Name (_ADR, 0x001f0000)
+
+	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
+	Field (LPC0, AnyAcc, NoLock, Preserve)
+	{
+		Offset (0x02),
+		PDID,	16,	// Device ID
+		Offset (0x40),
+		PMBS,	16,	// PMBASE
+		Offset (0x48),
+		GPBS,	16,	// GPIOBASE
+		Offset (0x60),	// Interrupt Routing Registers
+		PRTA,	8,
+		PRTB,	8,
+		PRTC,	8,
+		PRTD,	8,
+		Offset (0x68),
+		PRTE,	8,
+		PRTF,	8,
+		PRTG,	8,
+		PRTH,	8,
+
+		Offset (0x80),	// IO Decode Ranges
+		IOD0,	8,
+		IOD1,	8,
+	}
+
+	Device (DMAC)	// DMA Controller
+	{
+		Name (_HID, EISAID("PNP0200"))
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x00, 0x00, 0x01, 0x20)
+			IO (Decode16, 0x81, 0x81, 0x01, 0x11)
+			IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
+			IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
+			DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
+		})
+	}
+
+	Device (FWH)	// Firmware Hub
+	{
+		Name (_HID, EISAID("INT0800"))
+		Name (_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+		})
+	}
+
+	Device (HPET)
+	{
+		Name (_HID, EISAID("PNP0103"))
+		Name (_CID, 0x010CD041)
+
+		Name (BUF0, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0)
+		})
+
+		Method (_STA, 0)	// Device Status
+		{
+			If (HPTE) {
+				// Note: Ancient versions of Windows don't want
+				// to see the HPET in order to work right
+				If (LGreaterEqual(OSYS, 2001)) {
+					Return (0xf)	// Enable and show device
+				} Else {
+					Return (0xb)	// Enable and don't show device
+				}
+			}
+
+			Return (0x0)	// Not enabled, don't show.
+		}
+
+		Method (_CRS, 0, Serialized) // Current resources
+		{
+			If (HPTE) {
+				CreateDWordField (BUF0,
+					\_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
+
+				If (Lequal(HPAS, 1)) {
+					Store(0xfed01000, HPT0)
+				}
+
+				If (Lequal(HPAS, 2)) {
+					Store(0xfed02000, HPT0)
+				}
+
+				If (Lequal(HPAS, 3)) {
+					Store(0xfed03000, HPT0)
+				}
+			}
+
+			Return (BUF0)
+		}
+	}
+
+	Device(PIC)	// 8259 Interrupt Controller
+	{
+		Name (_HID,EISAID("PNP0000"))
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x20, 0x20, 0x01, 0x02)
+			IO (Decode16, 0x24, 0x24, 0x01, 0x02)
+			IO (Decode16, 0x28, 0x28, 0x01, 0x02)
+			IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
+			IO (Decode16, 0x30, 0x30, 0x01, 0x02)
+			IO (Decode16, 0x34, 0x34, 0x01, 0x02)
+			IO (Decode16, 0x38, 0x38, 0x01, 0x02)
+			IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
+			IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
+			IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
+			IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
+			IO (Decode16, 0xac, 0xac, 0x01, 0x02)
+			IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
+			IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
+			IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
+			IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
+			IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+			IRQNoFlags () { 2 }
+		})
+	}
+
+	Device(MATH)	// FPU
+	{
+		Name (_HID, EISAID("PNP0C04"))
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
+			IRQNoFlags() { 13 }
+		})
+	}
+
+	Device(LDRC)	// LPC device: Resource consumption
+	{
+		Name (_HID, EISAID("PNP0C02"))
+		Name (_UID, 2)
+
+		Name (RBUF, ResourceTemplate()
+		{
+			IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
+			IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
+			IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
+			IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
+			IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
+			IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
+			IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
+			IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
+			IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
+			IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
+			    0x1, 0xff)
+		})
+
+		Method (_CRS, 0, NotSerialized)
+		{
+			Return (RBUF)
+		}
+	}
+
+	Device (RTC)	// Real Time Clock
+	{
+		Name (_HID, EISAID("PNP0B00"))
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x70, 0x70, 1, 8)
+			//IRQNoFlags() { 8 }
+		})
+	}
+
+	Device (TIMR)	// Intel 8254 timer
+	{
+		Name (_HID, EISAID("PNP0100"))
+		Name (_CRS, ResourceTemplate() {
+			IO (Decode16, 0x40, 0x40, 0x01, 0x04)
+			IO (Decode16, 0x50, 0x50, 0x10, 0x04)
+			IRQNoFlags() {0}
+		})
+	}
+
+	#include "gpio.asl"
+	#include "irqlinks.asl"
+	#include <acpi/ec.asl>
+	#include <acpi/superio.asl>
+}
diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
new file mode 100644
index 0000000000..998133d9d9
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <soc/iomap.h>
+
+Scope (\)
+{
+	// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
+	OperationRegion (IO_T, SystemIO, 0x800, 0x10)
+	Field (IO_T, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x8),
+		TRP0, 8		// IO-Trap at 0x808
+	}
+
+	// Root Complex Register Block
+	OperationRegion (RCRB, SystemMemory, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+	Field (RCRB, DWordAcc, Lock, Preserve)
+	{
+		Offset (0x3404), // High Performance Timer Configuration
+		HPAS, 2, 	// Address Select
+		, 5,
+		HPTE, 1,	// Address Enable
+	}
+
+	/*
+	 * Check PCH type
+	 * Return 1 if PCH is WildcatPoint
+	 * Return 0 if PCH is LynxPoint
+	 */
+	Method (ISWP)
+	{
+		And (\_SB.PCI0.LPCB.PDID, 0xfff0, Local0)
+		If (LEqual (Local0, 0x9cc0)) {
+			Return (1)
+		} Else {
+			Return (0)
+		}
+	}
+}
+
+// High Definition Audio (Azalia) 0:1b.0
+#include "hda.asl"
+
+// ADSP/SST 0:13.0
+#include "adsp.asl"
+
+// PCI Express Ports 0:1c.x
+#include "pcie.asl"
+
+// USB EHCI 0:1d.0
+#include "ehci.asl"
+
+// USB XHCI 0:14.0
+#include "xhci.asl"
+
+// LPC Bridge 0:1f.0
+#include "lpc.asl"
+
+// SATA 0:1f.2
+#include "sata.asl"
+
+// SMBus 0:1f.3
+#include "smbus.asl"
+
+// Serial IO
+#include "serialio.asl"
+
+Method (_OSC, 4)
+{
+	/* Check for proper GUID */
+	If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+	{
+		/* Let OS control everything */
+		Return (Arg3)
+	}
+	Else
+	{
+		/* Unrecognized UUID */
+		CreateDWordField (Arg3, 0, CDW1)
+		Or (CDW1, 4, CDW1)
+		Return (Arg3)
+	}
+}
diff --git a/src/soc/intel/skylake/acpi/pci_irqs.asl b/src/soc/intel/skylake/acpi/pci_irqs.asl
new file mode 100644
index 0000000000..0c23e10a51
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/pci_irqs.asl
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// Mini-HD Audio		0:3.0
+			Package() { 0x0003ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 16 },
+			Package() { 0x001cffff, 1, 0, 17 },
+			Package() { 0x001cffff, 2, 0, 18 },
+			Package() { 0x001cffff, 3, 0, 19 },
+			// EHCI	  			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// Audio DSP (Smart Sound)	0:13.0
+			Package() { 0x0013ffff, 0, 0, 23 },
+			// XHCI	  			0:14.0
+			Package() { 0x0014ffff, 0, 0, 18 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 22 },
+			Package() { 0x001fffff, 1, 0, 18 },
+			Package() { 0x001fffff, 2, 0, 17 },
+			Package() { 0x001fffff, 3, 0, 16 },
+			// Serial IO                    0:15.0
+			Package() { 0x0015ffff, 0, 0, 20 },
+			Package() { 0x0015ffff, 1, 0, 21 },
+			Package() { 0x0015ffff, 2, 0, 21 },
+			Package() { 0x0015ffff, 3, 0, 21 },
+			// SDIO                         0:17.0
+			Package() { 0x0017ffff, 0, 0, 23 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// Mini-HD Audio		0:3.0
+			Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	  			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// Audio DSP (Smart Sound)	0:13.0
+			Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+			// XHCI	  			0:14.0
+			Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+			// Serial IO                    0:15.0
+			Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+			Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+			Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
+			Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
+			// SDIO                         0:17.0
+			Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+		})
+	}
+}
+
diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl
new file mode 100644
index 0000000000..a48bdde0e3
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/pcie.asl
@@ -0,0 +1,214 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Intel PCH PCIe support */
+
+Method (IRQM, 1, Serialized) {
+
+	/* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
+	Name (IQAA, Package() {
+		Package() { 0x0000ffff, 0, 0, 16 },
+		Package() { 0x0000ffff, 1, 0, 17 },
+		Package() { 0x0000ffff, 2, 0, 18 },
+		Package() { 0x0000ffff, 3, 0, 19 } })
+	Name (IQAP, Package() {
+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } })
+
+	/* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
+	Name (IQBA, Package() {
+		Package() { 0x0000ffff, 0, 0, 17 },
+		Package() { 0x0000ffff, 1, 0, 18 },
+		Package() { 0x0000ffff, 2, 0, 19 },
+		Package() { 0x0000ffff, 3, 0, 16 } })
+	Name (IQBP, Package() {
+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } })
+
+	/* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
+	Name (IQCA, Package() {
+		Package() { 0x0000ffff, 0, 0, 18 },
+		Package() { 0x0000ffff, 1, 0, 19 },
+		Package() { 0x0000ffff, 2, 0, 16 },
+		Package() { 0x0000ffff, 3, 0, 17 } })
+	Name (IQCP, Package() {
+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } })
+
+	/* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
+	Name (IQDA, Package() {
+		Package() { 0x0000ffff, 0, 0, 19 },
+		Package() { 0x0000ffff, 1, 0, 16 },
+		Package() { 0x0000ffff, 2, 0, 17 },
+		Package() { 0x0000ffff, 3, 0, 18 } })
+	Name (IQDP, Package() {
+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
+		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } })
+
+	Switch (ToInteger (Arg0)) {
+		/* PCIe Root Port 1 and 5 */
+		Case (Package() { 1, 5 }) {
+			If (PICM) {
+				Return (IQAA)
+			} Else {
+				Return (IQAP)
+			}
+		}
+
+		/* PCIe Root Port 2 and 6 */
+		Case (Package() { 2, 6 }) {
+			If (PICM) {
+				Return (IQBA)
+			} Else {
+				Return (IQBP)
+			}
+		}
+
+		/* PCIe Root Port 3 and 7 */
+		Case (Package() { 3, 7 }) {
+			If (PICM) {
+				Return (IQCA)
+			} Else {
+				Return (IQCP)
+			}
+		}
+
+		/* PCIe Root Port 4 and 8 */
+		Case (Package() { 4, 8 }) {
+			If (PICM) {
+				Return (IQDA)
+			} Else {
+				Return (IQDP)
+			}
+		}
+
+		Default {
+			If (PICM) {
+				Return (IQDA)
+			} Else {
+				Return (IQDP)
+			}
+		}
+	}
+}
+
+Device (RP01)
+{
+	Name (_ADR, 0x001c0000)
+
+	#include "pcie_port.asl"
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP02)
+{
+	Name (_ADR, 0x001c0001)
+
+	#include "pcie_port.asl"
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP03)
+{
+	Name (_ADR, 0x001c0002)
+
+	#include "pcie_port.asl"
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP04)
+{
+	Name (_ADR, 0x001c0003)
+
+	#include "pcie_port.asl"
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP05)
+{
+	Name (_ADR, 0x001c0004)
+
+	#include "pcie_port.asl"
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP06)
+{
+	Name (_ADR, 0x001c0005)
+
+	#include "pcie_port.asl"
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP07)
+{
+	Name (_ADR, 0x001c0006)
+
+	#include "pcie_port.asl"
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP08)
+{
+	Name (_ADR, 0x001c0007)
+
+	#include "pcie_port.asl"
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
diff --git a/src/soc/intel/skylake/acpi/pcie_port.asl b/src/soc/intel/skylake/acpi/pcie_port.asl
new file mode 100644
index 0000000000..32267461b7
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/pcie_port.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Included in each PCIe Root Port device */
+
+OperationRegion (RPCS, PCI_Config, 0x00, 0xFF)
+Field (RPCS, AnyAcc, NoLock, Preserve)
+{
+	Offset (0x4c),	// Link Capabilities
+	, 24,
+	RPPN, 8,	// Root Port Number
+}
diff --git a/src/soc/intel/skylake/acpi/platform.asl b/src/soc/intel/skylake/acpi/platform.asl
new file mode 100644
index 0000000000..f63168a745
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/platform.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method (TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method (_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice. */
+	Store (Arg0, PICM)
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method (_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method (_WAK, 1)
+{
+	Return (Package (){ 0, 0 })
+}
+
+Scope (\_SB)
+{
+	Method (_SWS)
+	{
+		/* Index into PM1 for device that caused wake */
+		Return (\PM1I)
+	}
+}
+
+Scope (\_GPE)
+{
+	Method (_SWS)
+	{
+		/* Index into GPE for device that caused wake */
+		Return (\GPEI)
+	}
+}
diff --git a/src/soc/intel/skylake/acpi/sata.asl b/src/soc/intel/skylake/acpi/sata.asl
new file mode 100644
index 0000000000..0af2a3f3f5
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/sata.asl
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Intel SATA Controller 0:1f.2
+Device (SATA)
+{
+	Name (_ADR, 0x001f0002)
+}
diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl
new file mode 100644
index 0000000000..7ffc671a74
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/serialio.asl
@@ -0,0 +1,627 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Intel Serial IO Devices in ACPI Mode
+
+// Serial IO Device BAR0 and BAR1 is 4KB
+#define SIO_BAR_LEN 0x1000
+
+// Put SerialIO device in D0 state
+// Arg0 - BAR1 of device
+// Arg1 - Set if device is in ACPI mode
+Method (LPD0, 2, Serialized)
+{
+	// PCI mode devices will be handled by OS PCI bus driver
+	If (LEqual (Arg1, 0)) {
+		Return
+	}
+
+	OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4)
+	Field (SPRT, DWordAcc, NoLock, Preserve)
+	{
+		SPCS, 32
+	}
+
+	And (SPCS, 0xFFFFFFFC, SPCS)
+	Store (SPCS, Local0) // Read back after writing
+}
+
+// Put SerialIO device in D3 state
+// Arg0 - BAR1 of device
+// Arg1 - Set if device is in ACPI mode
+Method (LPD3, 2, Serialized)
+{
+	// PCI mode devices will be handled by OS PCI bus driver
+	If (LEqual (Arg1, 0)) {
+		Return
+	}
+
+	OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4)
+	Field (SPRT, DWordAcc, NoLock, Preserve)
+	{
+		SPCS, 32
+	}
+
+	Or (SPCS, 0x3, SPCS)
+	Store (SPCS, Local0) // Read back after writing
+}
+
+// Serial IO Resource Consumption for BAR1
+Device (SIOR)
+{
+	Name (_HID, EISAID("PNP0C02"))
+	Name (_UID, 4)
+
+	Name (RBUF, ResourceTemplate()
+	{
+		// Serial IO BAR1 (PCI config space) resources
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D0) // SDMA
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D1) // I2C0
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D2) // I2C1
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D3) // SPI0
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D4) // SPI1
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D5) // UART0
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D6) // UART1
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D7) // SDIO
+	})
+
+	// Update BAR1 address and length if set in NVS
+	Method (_CRS, 0, NotSerialized)
+	{
+		// SDMA
+		If (LNotEqual (\S0B1, Zero)) {
+			CreateDwordField (^RBUF, ^B1D0._BAS, B0AD)
+			CreateDwordField (^RBUF, ^B1D0._LEN, B0LN)
+			Store (\S0B1, B0AD)
+			Store (SIO_BAR_LEN, B0LN)
+		}
+
+		// I2C0
+		If (LNotEqual (\S1B1, Zero)) {
+			CreateDwordField (^RBUF, ^B1D1._BAS, B1AD)
+			CreateDwordField (^RBUF, ^B1D1._LEN, B1LN)
+			Store (\S1B1, B1AD)
+			Store (SIO_BAR_LEN, B1LN)
+		}
+
+		// I2C1
+		If (LNotEqual (\S2B1, Zero)) {
+			CreateDwordField (^RBUF, ^B1D2._BAS, B2AD)
+			CreateDwordField (^RBUF, ^B1D2._LEN, B2LN)
+			Store (\S2B1, B2AD)
+			Store (SIO_BAR_LEN, B2LN)
+		}
+
+		// SPI0
+		If (LNotEqual (\S3B1, Zero)) {
+			CreateDwordField (^RBUF, ^B1D3._BAS, B3AD)
+			CreateDwordField (^RBUF, ^B1D3._LEN, B3LN)
+			Store (\S3B1, B3AD)
+			Store (SIO_BAR_LEN, B3LN)
+		}
+
+		// SPI1
+		If (LNotEqual (\S4B1, Zero)) {
+			CreateDwordField (^RBUF, ^B1D4._BAS, B4AD)
+			CreateDwordField (^RBUF, ^B1D4._LEN, B4LN)
+			Store (\S4B1, B4AD)
+			Store (SIO_BAR_LEN, B4LN)
+		}
+
+		// UART0
+		If (LNotEqual (\S5B1, Zero)) {
+			CreateDwordField (^RBUF, ^B1D5._BAS, B5AD)
+			CreateDwordField (^RBUF, ^B1D5._LEN, B5LN)
+			Store (\S5B1, B5AD)
+			Store (SIO_BAR_LEN, B5LN)
+		}
+
+		// UART1
+		If (LNotEqual (\S6B1, Zero)) {
+			CreateDwordField (^RBUF, ^B1D6._BAS, B6AD)
+			CreateDwordField (^RBUF, ^B1D6._LEN, B6LN)
+			Store (\S6B1, B6AD)
+			Store (SIO_BAR_LEN, B6LN)
+		}
+
+		// SDIO
+		If (LNotEqual (\S7B1, Zero)) {
+			CreateDwordField (^RBUF, ^B1D7._BAS, B7AD)
+			CreateDwordField (^RBUF, ^B1D7._LEN, B7LN)
+			Store (\S7B1, B7AD)
+			Store (SIO_BAR_LEN, B7LN)
+		}
+
+		Return (RBUF)
+	}
+}
+
+Device (SDMA)
+{
+	// Serial IO DMA Controller
+	Name (_HID, "INTL9C60")
+	Name (_UID, 1)
+	Name (_ADR, 0x00150000)
+
+	// BAR0 is assigned during PCI enumeration and saved into NVS
+	Name (RBUF, ResourceTemplate ()
+	{
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		// Update BAR0 address and length if set in NVS
+		If (LNotEqual (\S0B0, Zero)) {
+			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
+			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
+			Store (\S0B0, B0AD)
+			Store (SIO_BAR_LEN, B0LN)
+		}
+
+		Return (RBUF)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		If (LEqual (\S0EN, 0)) {
+			Return (0x0)
+		} Else {
+			Return (0xF)
+		}
+	}
+}
+
+Device (I2C0)
+{
+	// Serial IO I2C0 Controller
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3432")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C2")
+	}
+	Name (_UID, 1)
+	Name (_ADR, 0x00150001)
+
+	Name (SSCN, Package () { 432, 507, 30 })
+	Name (FMCN, Package () { 72, 160, 30 })
+
+	// BAR0 is assigned during PCI enumeration and saved into NVS
+	Name (RBUF, ResourceTemplate ()
+	{
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
+	})
+
+	// DMA channels are only used if Serial IO DMA controller is enabled
+	Name (DBUF, ResourceTemplate ()
+	{
+		FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx
+		FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		// Update BAR0 address and length if set in NVS
+		If (LNotEqual (\S1B0, Zero)) {
+			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
+			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
+			Store (\S1B0, B0AD)
+			Store (SIO_BAR_LEN, B0LN)
+		}
+
+		// Check if Serial IO DMA Controller is enabled
+		If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) {
+			Return (ConcatenateResTemplate (RBUF, DBUF))
+		} Else {
+			Return (RBUF)
+		}
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		If (LEqual (\S1EN, 0)) {
+			Return (0x0)
+		} Else {
+			Return (0xF)
+		}
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (\S1B1, \S1EN)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (\S1B1, \S1EN)
+	}
+}
+
+Device (I2C1)
+{
+	// Serial IO I2C1 Controller
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3433")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C3")
+	}
+	Name (_UID, 1)
+	Name (_ADR, 0x00150002)
+
+	Name (SSCN, Package () { 432, 507, 30 })
+	Name (FMCN, Package () { 72, 160, 30 })
+
+	// BAR0 is assigned during PCI enumeration and saved into NVS
+	Name (RBUF, ResourceTemplate ()
+	{
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
+	})
+
+	// DMA channels are only used if Serial IO DMA controller is enabled
+	Name (DBUF, ResourceTemplate ()
+	{
+		FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx
+		FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		// Update BAR0 address and length if set in NVS
+		If (LNotEqual (\S2B0, Zero)) {
+			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
+			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
+			Store (\S2B0, B0AD)
+			Store (SIO_BAR_LEN, B0LN)
+		}
+
+		// Check if Serial IO DMA Controller is enabled
+		If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) {
+			Return (ConcatenateResTemplate (RBUF, DBUF))
+		} Else {
+			Return (RBUF)
+		}
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		If (LEqual (\S2EN, 0)) {
+			Return (0x0)
+		} Else {
+			Return (0xF)
+		}
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (\S2B1, \S2EN)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (\S2B1, \S2EN)
+	}
+}
+
+Device (SPI0)
+{
+	// Serial IO SPI0 Controller
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3430")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C0")
+	}
+	Name (_UID, 1)
+	Name (_ADR, 0x00150003)
+
+	// BAR0 is assigned during PCI enumeration and saved into NVS
+	Name (RBUF, ResourceTemplate ()
+	{
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		// Update BAR0 address and length if set in NVS
+		If (LNotEqual (\S3B0, Zero)) {
+			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
+			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
+			Store (\S3B0, B0AD)
+			Store (SIO_BAR_LEN, B0LN)
+		}
+
+		Return (RBUF)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		If (LEqual (\S3EN, 0)) {
+			Return (0x0)
+		} Else {
+			Return (0xF)
+		}
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (\S3B1, \S3EN)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (\S3B1, \S3EN)
+	}
+}
+
+Device (SPI1)
+{
+	// Serial IO SPI1 Controller
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3431")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C1")
+	}
+	Name (_UID, 1)
+	Name (_ADR, 0x00150004)
+
+	// BAR0 is assigned during PCI enumeration and saved into NVS
+	Name (RBUF, ResourceTemplate ()
+	{
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
+	})
+
+	// DMA channels are only used if Serial IO DMA controller is enabled
+	Name (DBUF, ResourceTemplate ()
+	{
+		FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx
+		FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		// Update BAR0 address and length if set in NVS
+		If (LNotEqual (\S4B0, Zero)) {
+			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
+			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
+			Store (\S4B0, B0AD)
+			Store (SIO_BAR_LEN, B0LN)
+		}
+
+		// Check if Serial IO DMA Controller is enabled
+		If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) {
+			Return (ConcatenateResTemplate (RBUF, DBUF))
+		} Else {
+			Return (RBUF)
+		}
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		If (LEqual (\S4EN, 0)) {
+			Return (0x0)
+		} Else {
+			Return (0xF)
+		}
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (\S4B1, \S4EN)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (\S4B1, \S4EN)
+	}
+}
+
+Device (UAR0)
+{
+	// Serial IO UART0 Controller
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3434")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C4")
+	}
+	Name (_UID, 1)
+	Name (_ADR, 0x00150005)
+
+	// BAR0 is assigned during PCI enumeration and saved into NVS
+	Name (RBUF, ResourceTemplate ()
+	{
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13}
+	})
+
+	// DMA channels are only used if Serial IO DMA controller is enabled
+	Name (DBUF, ResourceTemplate ()
+	{
+		FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx
+		FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		// Update BAR0 address and length if set in NVS
+		If (LNotEqual (\S5B0, Zero)) {
+			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
+			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
+			Store (\S5B0, B0AD)
+			Store (SIO_BAR_LEN, B0LN)
+		}
+
+		// Check if Serial IO DMA Controller is enabled
+		If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) {
+			Return (ConcatenateResTemplate (RBUF, DBUF))
+		} Else {
+			Return (RBUF)
+		}
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		If (LEqual (\S5EN, 0)) {
+			Return (0x0)
+		} Else {
+			Return (0xF)
+		}
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (\S5B1, \S5EN)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (\S5B1, \S5EN)
+	}
+}
+
+Device (UAR1)
+{
+	// Serial IO UART1 Controller
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3435")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C5")
+	}
+	Name (_UID, 1)
+	Name (_ADR, 0x00150006)
+
+	// BAR0 is assigned during PCI enumeration and saved into NVS
+	Name (RBUF, ResourceTemplate ()
+	{
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13}
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		// Update BAR0 address and length if set in NVS
+		If (LNotEqual (\S6B0, Zero)) {
+			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
+			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
+			Store (\S6B0, B0AD)
+			Store (SIO_BAR_LEN, B0LN)
+		}
+
+		Return (RBUF)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		If (LEqual (\S6EN, 0)) {
+			Return (0x0)
+		} Else {
+			Return (0xF)
+		}
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (\S6B1, \S6EN)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (\S6B1, \S6EN)
+	}
+}
+
+Device (SDIO)
+{
+	// Serial IO SDIO Controller
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3436")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C6")
+	}
+	Name (_CID, "PNP0D40")
+	Name (_UID, 1)
+	Name (_ADR, 0x00170000)
+
+	// BAR0 is assigned during PCI enumeration and saved into NVS
+	Name (RBUF, ResourceTemplate ()
+	{
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {5}
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		// Update BAR0 address and length if set in NVS
+		If (LNotEqual (\S7B0, Zero)) {
+			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
+			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
+			Store (\S7B0, B0AD)
+			Store (SIO_BAR_LEN, B0LN)
+		}
+
+		Return (RBUF)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		If (LEqual (\S7EN, 0)) {
+			Return (0x0)
+		} Else {
+			Return (0xF)
+		}
+	}
+}
diff --git a/src/soc/intel/skylake/acpi/sleepstates.asl b/src/soc/intel/skylake/acpi/sleepstates.asl
new file mode 100644
index 0000000000..6fea862d86
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/sleepstates.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 })
+Name (\_S1, Package () { 0x1, 0x1, 0x0, 0x0 })
+Name (\_S2, Package () { 0x1, 0x1, 0x0, 0x0 })
+Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 })
+Name (\_S4, Package () { 0x6, 0x6, 0x0, 0x0 })
+Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 })
diff --git a/src/soc/intel/skylake/acpi/smbus.asl b/src/soc/intel/skylake/acpi/smbus.asl
new file mode 100644
index 0000000000..15bcfde69a
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/smbus.asl
@@ -0,0 +1,241 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Intel SMBus Controller 0:1f.3
+
+Device (SBUS)
+{
+	Name (_ADR, 0x001f0003)
+
+#ifdef ENABLE_SMBUS_METHODS
+	OperationRegion (SMBP, PCI_Config, 0x00, 0x100)
+	Field(SMBP, DWordAcc, NoLock, Preserve)
+	{
+		Offset(0x40),
+		,	2,
+		I2CE,	1
+	}
+
+	OperationRegion (SMBI, SystemIO, SMBUS_IO_BASE, 0x20)
+	Field (SMBI, ByteAcc, NoLock, Preserve)
+	{
+		HSTS,	8,	// Host Status
+		,	8,
+		HCNT,	8,	// Host Control
+		HCMD,	8,	// Host Command
+		TXSA,	8,	// Transmit Slave Address
+		DAT0,	8,	// Host Data 0
+		DAT1,	8,	// Host Data 1
+		HBDB,	8,	// Host Block Data Byte
+		PECK,	8,	// Packet Error Check
+		RXSA,	8,	// Receive Slave Address
+		RXDA,	16,	// Receive Slave Data
+		AUXS,	8,	// Auxiliary Status
+		AUXC,	8,	// Auxiliary Control
+		SLPC,	8,	// SMLink Pin Control
+		SBPC,	8,	// SMBus Pin Control
+		SSTS,	8,	// Slave Status
+		SCMD,	8,	// Slave Command
+		NADR,	8,	// Notify Device Address
+		NDLB,	8,	// Notify Data Low Byte
+		NDLH,	8,	// Notify Data High Byte
+	}
+
+	// Kill all SMBus communication
+	Method (KILL, 0, Serialized)
+	{
+		Or (HCNT, 0x02, HCNT)	// Send Kill
+		Or (HSTS, 0xff, HSTS)	// Clean Status
+	}
+
+	// Check if last operation completed
+	// return	Failure = 0, Success = 1
+	Method (CMPL, 0, Serialized)
+	{
+		Store (4000, Local0)		// Timeout 200ms in 50us steps
+		While (Local0) {
+			If (And(HSTS, 0x02)) {	// Completion Status?
+				Return (1)	// Operation Completed
+			} Else {
+				Stall (50)
+				Decrement (Local0)
+				If (LEqual(Local0, 0)) {
+					KILL()
+				}
+			}
+		}
+
+		Return (0)		//  Failure
+	}
+
+
+	// Wait for SMBus to become ready
+	Method (SRDY, 0, Serialized)
+	{
+		Store (200, Local0)	// Timeout 200ms
+		While (Local0) {
+			If (And(HSTS, 0x40)) {		// IN_USE?
+				Sleep(1)		// Wait 1ms
+				Decrement(Local0)	// timeout--
+				If (LEqual(Local0, 0)) {
+					Return (1)
+				}
+			} Else {
+				Store (0, Local0)	// We're ready
+			}
+		}
+
+		Store (4000, Local0)	// Timeout 200ms (50us * 4000)
+		While (Local0) {
+			If (And (HSTS, 0x01)) {		// Host Busy?
+				Stall(50)		// Wait 50us
+				Decrement(Local0)	// timeout--
+				If (LEqual(Local0, 0)) {
+					KILL()
+				}
+			} Else {
+				Return (0)		// Success
+			}
+		}
+
+		Return (1)		// Failure
+	}
+
+	// SMBus Send Byte
+	// Arg0:	Address
+	// Arg1:	Data
+	// Return:	1 = Success, 0=Failure
+
+	Method (SSXB, 2, Serialized)
+	{
+
+		// Is the SMBus Controller Ready?
+		If (SRDY()) {
+			Return (0)
+		}
+
+		// Send Byte
+		Store (0, I2CE)		// SMBus Enable
+		Store (0xbf, HSTS)
+		Store (Arg0, TXSA)	// Write Address
+		Store (Arg1, HCMD)	// Write Data
+
+		Store (0x48, HCNT)	// Start + Byte Data Protocol
+
+		If (CMPL()) {
+			Or (HSTS, 0xff, HSTS)	// Clean up
+			Return (1)		// Success
+		}
+
+		Return (0)
+	}
+
+
+	// SMBus Receive Byte
+	// Arg0:	Address
+	// Return:	0xffff = Failure, Data (8bit) = Success
+
+	Method (SRXB, 2, Serialized)
+	{
+
+		// Is the SMBus Controller Ready?
+		If (SRDY()) {
+			Return (0xffff)
+		}
+
+		// Receive Byte
+		Store (0, I2CE)		// SMBus Enable
+		Store (0xbf, HSTS)
+		Store (Or (Arg0, 1), TXSA)	// Write Address
+
+		Store (0x44, HCNT)	// Start
+
+		If (CMPL()) {
+			Or (HSTS, 0xff, HSTS)	// Clean up
+			Return (DAT0)		// Success
+		}
+
+		Return (0xffff)
+	}
+
+
+	// SMBus Write Byte
+	// Arg0:	Address
+	// Arg1:	Command
+	// Arg2:	Data
+	// Return:	1 = Success, 0=Failure
+
+	Method (SWRB, 3, Serialized)
+	{
+
+		// Is the SMBus Controller Ready?
+		If (SRDY()) {
+			Return (0)
+		}
+
+		// Send Byte
+		Store (0, I2CE)		// SMBus Enable
+		Store (0xbf, HSTS)
+		Store (Arg0, TXSA)	// Write Address
+		Store (Arg1, HCMD)	// Write Command
+		Store (Arg2, DAT0)	// Write Data
+
+		Store (0x48, HCNT)	// Start + Byte Protocol
+
+		If (CMPL()) {
+			Or (HSTS, 0xff, HSTS)	// Clean up
+			Return (1)		// Success
+		}
+
+		Return (0)
+	}
+
+
+	// SMBus Read Byte
+	// Arg0:	Address
+	// Arg1:	Command
+	// Return:	0xffff = Failure, Data (8bit) = Success
+
+	Method (SRDB, 2, Serialized)
+	{
+
+		// Is the SMBus Controller Ready?
+		If (SRDY()) {
+			Return (0xffff)
+		}
+
+		// Receive Byte
+		Store (0, I2CE)			// SMBus Enable
+		Store (0xbf, HSTS)
+		Store (Or (Arg0, 1), TXSA)	// Write Address
+		Store (Arg1, HCMD)		// Command
+
+		Store (0x48, HCNT)		// Start
+
+		If (CMPL()) {
+			Or (HSTS, 0xff, HSTS)	// Clean up
+			Return (DAT0)		// Success
+		}
+
+		Return (0xffff)
+	}
+#endif
+}
+
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
new file mode 100644
index 0000000000..c2049ea2e3
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -0,0 +1,213 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <soc/iomap.h>
+
+Name (_HID, EISAID ("PNP0A08"))	// PCIe
+Name (_CID, EISAID ("PNP0A03"))	// PCI
+
+Name (_ADR, 0)
+Name (_BBN, 0)
+
+Device (MCHC)
+{
+	Name (_ADR, 0x00000000)	// 0:0.0
+
+	OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
+	Field (MCHP, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0x70),	// ME Base Address
+		MEBA,	 64,
+		Offset (0xa0),	// Top of Used Memory
+		TOM,	 64,
+		Offset (0xbc),	// Top of Low Used Memory
+		TLUD,	 32,
+	}
+}
+
+// Current Resource Settings
+
+Method (_CRS, 0, Serialized)
+{
+	Name (MCRS, ResourceTemplate()
+	{
+		// Bus Numbers
+		WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
+
+		// IO Region 0
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
+
+		// PCI Config Space
+		Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		// IO Region 1
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
+
+		// VGA memory (0xa0000-0xbffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000,,, ASEG)
+
+		// OPROM reserved (0xc0000-0xc3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000,,, OPR0)
+
+		// OPROM reserved (0xc4000-0xc7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000,,, OPR1)
+
+		// OPROM reserved (0xc8000-0xcbfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000,,, OPR2)
+
+		// OPROM reserved (0xcc000-0xcffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000,,, OPR3)
+
+		// OPROM reserved (0xd0000-0xd3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000,,, OPR4)
+
+		// OPROM reserved (0xd4000-0xd7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000,,, OPR5)
+
+		// OPROM reserved (0xd8000-0xdbfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000,,, OPR6)
+
+		// OPROM reserved (0xdc000-0xdffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000,,, OPR7)
+
+		// BIOS Extension (0xe0000-0xe3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000,,, ESG0)
+
+		// BIOS Extension (0xe4000-0xe7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000,,, ESG1)
+
+		// BIOS Extension (0xe8000-0xebfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000,,, ESG2)
+
+		// BIOS Extension (0xec000-0xeffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000,,, ESG3)
+
+		// System BIOS (0xf0000-0xfffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000,,, FSEG)
+
+		// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000,,, PM01)
+
+		// TPM Area (0xfed40000-0xfed44fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
+				0x00005000,,, TPMR)
+	})
+
+	// Find PCI resource area in MCRS
+	CreateDwordField(MCRS, PM01._MIN, PMIN)
+	CreateDwordField(MCRS, PM01._MAX, PMAX)
+	CreateDwordField(MCRS, PM01._LEN, PLEN)
+
+	// Fix up PCI memory region
+	// Start with Top of Lower Usable DRAM
+	Store (^MCHC.TLUD, Local0)
+	Store (^MCHC.MEBA, Local1)
+
+	// Check if ME base is equal
+	If (LEqual (Local0, Local1)) {
+		// Use Top Of Memory instead
+		Store (^MCHC.TOM, Local0)
+	}
+
+	Store (Local0, PMIN)
+	Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
+	Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+	Return (MCRS)
+}
+
+/* PCI Device Resource Consumption */
+Device (PDRC)
+{
+	Name (_HID, EISAID("PNP0C02"))
+	Name (_UID, 1)
+
+	Name (PDRS, ResourceTemplate() {
+		Memory32Fixed (ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+		Memory32Fixed (ReadWrite, MCH_BASE_ADDRESS, MCH_BASE_SIZE)
+		Memory32Fixed (ReadWrite, DMI_BASE_ADDRESS, DMI_BASE_SIZE)
+		Memory32Fixed (ReadWrite, EP_BASE_ADDRESS, EP_BASE_SIZE)
+		Memory32Fixed (ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+		Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE)
+		Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE)
+	})
+
+	// Current Resource Settings
+	Method (_CRS, 0, Serialized)
+	{
+		Return (PDRS)
+	}
+}
+
+/* PCI IRQ assignment */
+#include "pci_irqs.asl"
+
+/* Configurable TDP */
+#include "ctdp.asl"
diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl
new file mode 100644
index 0000000000..c41275ccd2
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/xhci.asl
@@ -0,0 +1,371 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// XHCI Controller 0:14.0
+
+Device (XHCI)
+{
+	Name (_ADR, 0x00140000)
+
+	Name (PLSD, 5) // Port Link State - RxDetect
+	Name (PLSP, 7) // Port Link State - Polling
+
+	OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
+	Field (XPRT, AnyAcc, NoLock, Preserve)
+	{
+		Offset (0x0),
+		DVID, 16,
+		Offset (0x10),
+		, 16,
+		XMEM, 16, // MEM_BASE
+		Offset (0x40),
+		, 11,
+		SWAI, 1,
+		, 20,
+		Offset (0x44),
+		, 12,
+		SAIP, 2,
+		, 18,
+		Offset (0x74),
+		D0D3, 2,
+		, 6,
+		PMEE, 1,  // PME_EN
+		, 6,
+		PMES, 1,  // PME_STS
+		Offset (0xb0),
+		, 13,
+		MB13, 1,
+		MB14, 1,
+		Offset (0xd0),
+		PR2R, 32,  // USB2PR
+		PR2M, 32,  // USB2PRM
+		PR3R, 32,  // USB3PR
+		PR3M, 32,  // USB3PRM
+	}
+
+	// Clear status bits
+	Method (LPCL, 0, Serialized)
+	{
+		OperationRegion (XREG, SystemMemory,
+				 ShiftLeft (^XMEM, 16), 0x600)
+		Field (XREG, DWordAcc, Lock, Preserve)
+		{
+			Offset (0x510), // PORTSCNUSB3[0]
+			PSC0, 32,
+			Offset (0x520), // PORTSCNUSB3[1]
+			PSC1, 32,
+			Offset (0x530), // PORTSCNUSB3[2]
+			PSC2, 32,
+			Offset (0x540), // PORTSCNUSB3[3]
+			PSC3, 32,
+		}
+
+		// Port Enabled/Disabled (Bit 1)
+		Name (PEDB, ShiftLeft (1, 1))
+
+		// Change Status (Bits 23:17)
+		Name (CHST, ShiftLeft (0x7f, 17))
+
+		// Port 0
+		And (PSC0, Not (PEDB), Local0)
+		Or (Local0, CHST, PSC0)
+
+		// Port 1
+		And (PSC1, Not (PEDB), Local0)
+		Or (Local0, CHST, PSC1)
+
+		// Port 2
+		And (PSC2, Not (PEDB), Local0)
+		Or (Local0, CHST, PSC2)
+
+		// Port 3
+		And (PSC3, Not (PEDB), Local0)
+		Or (Local0, CHST, PSC3)
+	}
+
+	Method (LPS0, 0, Serialized)
+	{
+		OperationRegion (XREG, SystemMemory,
+				 ShiftLeft (^XMEM, 16), 0x600)
+		Field (XREG, DWordAcc, Lock, Preserve)
+		{
+			Offset (0x510), // PORTSCNUSB3
+			, 5,
+			PLS1, 4,	// [8:5] Port Link State
+			PPR1, 1,	// [9] Port Power
+			, 7,
+			CSC1, 1,	// [17] Connect Status Change
+			, 1,
+			WRC1, 1,	// [19] Warm Port Reset Change
+			, 11,
+			WPR1, 1,	// [31] Warm Port Reset
+			Offset (0x520), // PORTSCNUSB3
+			, 5,
+			PLS2, 4,	// [8:5] Port Link State
+			PPR2, 1,	// [9] Port Power
+			, 7,
+			CSC2, 1,	// [17] Connect Status Change
+			, 1,
+			WRC2, 1,	// [19] Warm Port Reset Change
+			, 11,
+			WPR2, 1,	// [31] Warm Port Reset
+			Offset (0x530), // PORTSCNUSB3
+			, 5,
+			PLS3, 4,	// [8:5] Port Link State
+			PPR3, 1,	// [9] Port Power
+			, 7,
+			CSC3, 1,	// [17] Connect Status Change
+			, 1,
+			WRC3, 1,	// [19] Warm Port Reset Change
+			, 11,
+			WPR3, 1,	// [31] Warm Port Reset
+			Offset (0x540), // PORTSCNUSB3
+			, 5,
+			PLS4, 4,	// [8:5] Port Link State
+			PPR4, 1,	// [9] Port Power
+			, 7,
+			CSC4, 1,	// [17] Connect Status Change
+			, 1,
+			WRC4, 1,	// [19] Warm Port Reset Change
+			, 11,
+			WPR4, 1,	// [31] Warm Port Reset
+		}
+
+		// Wait for all powered ports to finish polling
+		Store (10, Local0)
+		While (LOr (LOr (LAnd (LEqual (PPR1, 1), LEqual (PLS1, PLSP)),
+				 LAnd (LEqual (PPR2, 1), LEqual (PLS2, PLSP))),
+			    LOr (LAnd (LEqual (PPR3, 1), LEqual (PLS3, PLSP)),
+				 LAnd (LEqual (PPR4, 1), LEqual (PLS4, PLSP)))))
+		{
+			If (LEqual (Local0, 0)) {
+				Break
+			}
+			Decrement (Local0)
+			Stall (10)
+		}
+
+		// For each USB3 Port:
+		//   If port is disconnected (PLS=5 PP=1 CSC=0)
+		//     1) Issue warm reset (WPR=1)
+		//     2) Poll for warm reset complete (WRC=0)
+		//     3) Write 1 to port status to clear
+
+		// Local# indicate if port is reset
+		Store (0, Local1)
+		Store (0, Local2)
+		Store (0, Local3)
+		Store (0, Local4)
+
+		If (LAnd (LEqual (PLS1, PLSD),
+		          LAnd (LEqual (CSC1, 0), LEqual (PPR1, 1)))) {
+			Store (1, WPR1)	      // Issue warm reset
+			Store (1, Local1)
+		}
+		If (LAnd (LEqual (PLS2, PLSD),
+		          LAnd (LEqual (CSC2, 0), LEqual (PPR2, 1)))) {
+			Store (1, WPR2)	      // Issue warm reset
+			Store (1, Local2)
+		}
+		If (LAnd (LEqual (PLS3, PLSD),
+		          LAnd (LEqual (CSC3, 0), LEqual (PPR3, 1)))) {
+			Store (1, WPR3)	      // Issue warm reset
+			Store (1, Local3)
+		}
+		If (LAnd (LEqual (PLS4, PLSD),
+		          LAnd (LEqual (CSC4, 0), LEqual (PPR4, 1)))) {
+			Store (1, WPR4)	      // Issue warm reset
+			Store (1, Local4)
+		}
+
+		// Poll for warm reset complete on all ports that were reset
+		Store (10, Local0)
+		While (LOr (LOr (LAnd (LEqual (Local1, 1), LEqual (WRC1, 0)),
+				 LAnd (LEqual (Local2, 1), LEqual (WRC2, 0))),
+			    LOr (LAnd (LEqual (Local3, 1), LEqual (WRC3, 0)),
+			         LAnd (LEqual (Local4, 1), LEqual (WRC4, 0)))))
+		{
+			If (LEqual (Local0, 0)) {
+				Break
+			}
+			Decrement (Local0)
+			Stall (10)
+		}
+
+		// Clear status bits in all ports
+		LPCL ()
+	}
+
+	Method (_PSC, 0, NotSerialized)
+	{
+		Return (^D0D3)
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		If (LEqual (^DVID, 0xFFFF)) {
+			Return ()
+		}
+		If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
+			Return ()
+		}
+
+		OperationRegion (XREG, SystemMemory,
+				 Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200)
+		Field (XREG, DWordAcc, Lock, Preserve)
+		{
+			Offset (0x0e0), // AUX Reset Control 1
+			, 15,
+			AX15, 1,
+			Offset (0x154), // AUX Domain PM Control Register 2
+			, 31,
+			CLK2, 1,
+			Offset (0x16c), // AUX Clock Control
+			, 2,
+			CLK0, 1,
+			, 11,
+			CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable
+		}
+
+		// If device is in D3, set back to D0
+		Store (^D0D3, Local0)
+		if (LEqual (Local0, 3)) {
+			Store (0, ^D0D3)
+		}
+
+		if (LNot (\ISWP())) {
+			// Clear PCI 0xB0[14:13]
+			Store (0, ^MB13)
+			Store (0, ^MB14)
+
+			// Clear MMIO 0x816C[14,2]
+			Store (0, CLK0)
+			Store (0, CLK1)
+
+			// Set MMIO 0x8154[31]
+			Store (1, CLK2)
+
+			// Handle per-port reset if needed
+			LPS0 ()
+
+			// Set MMIO 0x80e0[15]
+			Store (1, AX15)
+
+			// Clear PCI CFG offset 0x40[11]
+			Store (0, ^SWAI)
+
+			// Clear PCI CFG offset 0x44[13:12]
+			Store (0, ^SAIP)
+		}
+
+		Return ()
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		If (LEqual (^DVID, 0xFFFF)) {
+			Return ()
+		}
+		If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
+			Return ()
+		}
+
+		OperationRegion (XREG, SystemMemory,
+				 Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200)
+		Field (XREG, DWordAcc, Lock, Preserve)
+		{
+			Offset (0x0e0), // AUX Reset Control 1
+			, 15,
+			AX15, 1,
+			Offset (0x154), // AUX Domain PM Control Register 2
+			, 31,
+			CLK2, 1,
+			Offset (0x16c), // AUX Clock Control
+			, 2,
+			CLK0, 1,
+			, 11,
+			CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable
+		}
+
+		Store (1, ^PMES) // Clear PME Status
+		Store (1, ^PMEE) // Enable PME
+
+		// If device is in D3, set back to D0
+		Store (^D0D3, Local0)
+		if (LEqual (Local0, 3)) {
+			Store (0, ^D0D3)
+		}
+
+		if (LNot (\ISWP())) {
+			// Set PCI 0xB0[14:13]
+			Store (1, ^MB13)
+			Store (1, ^MB14)
+
+			// Set MMIO 0x816C[14,2]
+			Store (1, CLK0)
+			Store (1, CLK1)
+
+			// Clear MMIO 0x8154[31]
+			Store (0, CLK2)
+
+			// Clear MMIO 0x80e0[15]
+			Store (0, AX15)
+
+			// Set PCI CFG offset 0x40[11]
+			Store (1, ^SWAI)
+
+			// Set PCI CFG offset 0x44[13:12]
+			Store (1, ^SAIP)
+		}
+
+		// Put device in D3
+		Store (3, ^D0D3)
+
+		Return ()
+	}
+
+	Name (_PRW, Package(){ 0x6d, 3 })
+
+	// Leave USB ports on for to allow Wake from USB
+
+	Method(_S3D,0)	// Highest D State in S3 State
+	{
+		Return (3)
+	}
+
+	Method(_S4D,0)	// Highest D State in S4 State
+	{
+		Return (3)
+	}
+
+	Device (HUB7)
+	{
+		Name (_ADR, 0x00000000)
+
+		// How many are there?
+		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
+		Device (PRT2) { Name (_ADR, 2) } // USB Port 1
+		Device (PRT3) { Name (_ADR, 3) } // USB Port 2
+		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
+		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
+		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+	}
+}
+