diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-09-23 18:01:45 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-10-14 18:33:40 +0000 |
| commit | aa1b6b06ef506eeb4cc73139b473a0aeb9ee26ba (patch) | |
| tree | 7ba7dc1498bb459018ee258cc500970b3883ff94 /src/soc/intel/skylake/acpi/xhci.asl | |
| parent | 909c512c88bd7de4d5c5e7e035f162cd1a039407 (diff) | |
skylake: ACPI: Fix compiler warnings with iasl-20150717
Updating to a new IASL introduces a lot of warnings that are
not serious issues but can be fixed with some reworks.
- Method local variables that are set but never used now warn,
when needing to read back a register the ordering is now changed
to set the value in Local0 first so the compiler does not complain.
- Methods that create an object must be serialized
- A ResourceTemplate declared inside a _CRS with a named variable
does not seem to be able to compile without a warning. To fix
this move the ResourceTemplate outside the _CRS method.
- The DPTF CPU code was still using the old legacy \_PR.CPUx
instead of the new \_PR.CPxx definitions.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=build glados with iasl-20150717 and see no warnings
Original-Change-Id: I4a66c7eb6495aac4ae1aa42100c846725c1a04d2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302168
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia3af802ca2faab4f1c59e73f2ce31a65c7e862e0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11812
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Diffstat (limited to 'src/soc/intel/skylake/acpi/xhci.asl')
| -rw-r--r-- | src/soc/intel/skylake/acpi/xhci.asl | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 5e4908780b..72c9dc26c3 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -79,7 +79,8 @@ Device (XHCI) /* If device is in D3, set back to D0 */ If (LEqual (^D0D3, 3)) { - Store (Zero, ^D0D3) + Store (Zero, Local0) + Store (Local0, ^D0D3) Store (^D0D3, Local0) } @@ -122,7 +123,8 @@ Device (XHCI) /* If device is in D3, set back to D0 */ If (LEqual (^D0D3, 3)) { - Store (Zero, ^D0D3) + Store (Zero, Local0) + Store (Local0, ^D0D3) Store (^D0D3, Local0) } @@ -130,7 +132,8 @@ Device (XHCI) Store (3, ^UPSW) /* Now put device in D3 */ - Store (3, ^D0D3) + Store (3, Local0) + Store (Local0, ^D0D3) Store (^D0D3, Local0) /* |