soc/intel: Add Skylake SOC support

Add the files to support the Skylake SOC.
Matches chromium tree at 927026db

BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform

Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 124 insertions, 174 deletions

diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl
index c41275ccd2..f0ee414b52 100644
--- a/src/soc/intel/skylake/acpi/xhci.asl
+++ b/src/soc/intel/skylake/acpi/xhci.asl
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2007-2009 coresystems GmbH
  * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -15,17 +16,17 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc.
  */
 
-// XHCI Controller 0:14.0
+/* XHCI Controller 0:14.0 */
 
 Device (XHCI)
 {
 	Name (_ADR, 0x00140000)
 
-	Name (PLSD, 5) // Port Link State - RxDetect
-	Name (PLSP, 7) // Port Link State - Polling
+	Name (PLSD, 5) /* Port Link State - RxDetect */
+	Name (PLSP, 7) /* Port Link State - Polling */
 
 	OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
 	Field (XPRT, AnyAcc, NoLock, Preserve)
@@ -34,68 +35,74 @@ Device (XHCI)
 		DVID, 16,
 		Offset (0x10),
 		, 16,
-		XMEM, 16, // MEM_BASE
-		Offset (0x40),
-		, 11,
-		SWAI, 1,
-		, 20,
-		Offset (0x44),
-		, 12,
-		SAIP, 2,
-		, 18,
+		XMEM, 16,	/* MEM_BASE */
 		Offset (0x74),
 		D0D3, 2,
 		, 6,
-		PMEE, 1,  // PME_EN
+		PMEE, 1,	/* PME_EN */
 		, 6,
-		PMES, 1,  // PME_STS
+		PMES, 1,	/* PME_STS */
+		Offset (0xA8),
+		, 13,
+		MW13, 1,
+		MW14, 1,
+		, 17,
 		Offset (0xb0),
 		, 13,
 		MB13, 1,
 		MB14, 1,
+		, 17,
 		Offset (0xd0),
-		PR2R, 32,  // USB2PR
-		PR2M, 32,  // USB2PRM
-		PR3R, 32,  // USB3PR
-		PR3M, 32,  // USB3PRM
+		PR2, 32,	/* USB2PR */
+		PR2M, 32,	/* USB2PRM */
+		PR3, 32,	/* USB3PR */
+		PR3M, 32,	/* USB3PRM */
+	}
+
+	Method (USRA,0){
+		Return(11)
 	}
 
-	// Clear status bits
+	Method (SSPA,0){
+		Return (13)
+	}
+
+	/* Clear status bits */
 	Method (LPCL, 0, Serialized)
 	{
 		OperationRegion (XREG, SystemMemory,
-				 ShiftLeft (^XMEM, 16), 0x600)
+			 ShiftLeft (^XMEM, 16), 0x600)
 		Field (XREG, DWordAcc, Lock, Preserve)
 		{
-			Offset (0x510), // PORTSCNUSB3[0]
+			Offset (0x510), /* PORTSCNUSB3[0]*/
 			PSC0, 32,
-			Offset (0x520), // PORTSCNUSB3[1]
+			Offset (0x520), /* PORTSCNUSB3[1]*/
 			PSC1, 32,
-			Offset (0x530), // PORTSCNUSB3[2]
+			Offset (0x530), /* PORTSCNUSB3[2]*/
 			PSC2, 32,
-			Offset (0x540), // PORTSCNUSB3[3]
+			Offset (0x540), /* PORTSCNUSB3[3]*/
 			PSC3, 32,
 		}
 
-		// Port Enabled/Disabled (Bit 1)
+		/* Port Enabled/Disabled (Bit 1)*/
 		Name (PEDB, ShiftLeft (1, 1))
 
-		// Change Status (Bits 23:17)
+		/* Change Status (Bits 23:17)*/
 		Name (CHST, ShiftLeft (0x7f, 17))
 
-		// Port 0
+		/* Port 0 */
 		And (PSC0, Not (PEDB), Local0)
 		Or (Local0, CHST, PSC0)
 
-		// Port 1
+		/* Port 1 */
 		And (PSC1, Not (PEDB), Local0)
 		Or (Local0, CHST, PSC1)
 
-		// Port 2
+		/* Port 2 */
 		And (PSC2, Not (PEDB), Local0)
 		Or (Local0, CHST, PSC2)
 
-		// Port 3
+		/* Port 3 */
 		And (PSC3, Not (PEDB), Local0)
 		Or (Local0, CHST, PSC3)
 	}
@@ -148,7 +155,7 @@ Device (XHCI)
 			WPR4, 1,	// [31] Warm Port Reset
 		}
 
-		// Wait for all powered ports to finish polling
+		/* Wait for all powered ports to finish polling*/
 		Store (10, Local0)
 		While (LOr (LOr (LAnd (LEqual (PPR1, 1), LEqual (PLS1, PLSP)),
 				 LAnd (LEqual (PPR2, 1), LEqual (PLS2, PLSP))),
@@ -162,13 +169,13 @@ Device (XHCI)
 			Stall (10)
 		}
 
-		// For each USB3 Port:
-		//   If port is disconnected (PLS=5 PP=1 CSC=0)
-		//     1) Issue warm reset (WPR=1)
-		//     2) Poll for warm reset complete (WRC=0)
-		//     3) Write 1 to port status to clear
+		/* For each USB3 Port:*/
+		/*   If port is disconnected (PLS=5 PP=1 CSC=0)*/
+		/*     1) Issue warm reset (WPR=1)*/
+		/*     2) Poll for warm reset complete (WRC=0)*/
+		/*     3) Write 1 to port status to clear*/
 
-		// Local# indicate if port is reset
+		/* Local# indicate if port is reset*/
 		Store (0, Local1)
 		Store (0, Local2)
 		Store (0, Local3)
@@ -176,26 +183,26 @@ Device (XHCI)
 
 		If (LAnd (LEqual (PLS1, PLSD),
 		          LAnd (LEqual (CSC1, 0), LEqual (PPR1, 1)))) {
-			Store (1, WPR1)	      // Issue warm reset
+			Store (1, WPR1)	      /* Issue warm reset*/
 			Store (1, Local1)
 		}
 		If (LAnd (LEqual (PLS2, PLSD),
 		          LAnd (LEqual (CSC2, 0), LEqual (PPR2, 1)))) {
-			Store (1, WPR2)	      // Issue warm reset
+			Store (1, WPR2)	      /* Issue warm reset*/
 			Store (1, Local2)
 		}
 		If (LAnd (LEqual (PLS3, PLSD),
 		          LAnd (LEqual (CSC3, 0), LEqual (PPR3, 1)))) {
-			Store (1, WPR3)	      // Issue warm reset
+			Store (1, WPR3)	      /* Issue warm reset*/
 			Store (1, Local3)
 		}
 		If (LAnd (LEqual (PLS4, PLSD),
 		          LAnd (LEqual (CSC4, 0), LEqual (PPR4, 1)))) {
-			Store (1, WPR4)	      // Issue warm reset
+			Store (1, WPR4)	      /* Issue warm reset*/
 			Store (1, Local4)
 		}
 
-		// Poll for warm reset complete on all ports that were reset
+		/* Poll for warm reset complete on all ports that were reset*/
 		Store (10, Local0)
 		While (LOr (LOr (LAnd (LEqual (Local1, 1), LEqual (WRC1, 0)),
 				 LAnd (LEqual (Local2, 1), LEqual (WRC2, 0))),
@@ -209,7 +216,7 @@ Device (XHCI)
 			Stall (10)
 		}
 
-		// Clear status bits in all ports
+		/* Clear status bits in all ports */
 		LPCL ()
 	}
 
@@ -220,152 +227,95 @@ Device (XHCI)
 
 	Method (_PS0, 0, Serialized)
 	{
-		If (LEqual (^DVID, 0xFFFF)) {
-			Return ()
-		}
-		If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
-			Return ()
-		}
-
-		OperationRegion (XREG, SystemMemory,
-				 Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200)
-		Field (XREG, DWordAcc, Lock, Preserve)
-		{
-			Offset (0x0e0), // AUX Reset Control 1
-			, 15,
-			AX15, 1,
-			Offset (0x154), // AUX Domain PM Control Register 2
-			, 31,
-			CLK2, 1,
-			Offset (0x16c), // AUX Clock Control
-			, 2,
-			CLK0, 1,
-			, 11,
-			CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable
-		}
-
-		// If device is in D3, set back to D0
-		Store (^D0D3, Local0)
-		if (LEqual (Local0, 3)) {
-			Store (0, ^D0D3)
-		}
-
-		if (LNot (\ISWP())) {
-			// Clear PCI 0xB0[14:13]
-			Store (0, ^MB13)
-			Store (0, ^MB14)
-
-			// Clear MMIO 0x816C[14,2]
-			Store (0, CLK0)
-			Store (0, CLK1)
-
-			// Set MMIO 0x8154[31]
-			Store (1, CLK2)
-
-			// Handle per-port reset if needed
-			LPS0 ()
-
-			// Set MMIO 0x80e0[15]
-			Store (1, AX15)
-
-			// Clear PCI CFG offset 0x40[11]
-			Store (0, ^SWAI)
-
-			// Clear PCI CFG offset 0x44[13:12]
-			Store (0, ^SAIP)
-		}
-
-		Return ()
 	}
-
 	Method (_PS3, 0, Serialized)
 	{
-		If (LEqual (^DVID, 0xFFFF)) {
-			Return ()
-		}
-		If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
-			Return ()
-		}
-
-		OperationRegion (XREG, SystemMemory,
-				 Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200)
-		Field (XREG, DWordAcc, Lock, Preserve)
-		{
-			Offset (0x0e0), // AUX Reset Control 1
-			, 15,
-			AX15, 1,
-			Offset (0x154), // AUX Domain PM Control Register 2
-			, 31,
-			CLK2, 1,
-			Offset (0x16c), // AUX Clock Control
-			, 2,
-			CLK0, 1,
-			, 11,
-			CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable
-		}
-
-		Store (1, ^PMES) // Clear PME Status
-		Store (1, ^PMEE) // Enable PME
-
-		// If device is in D3, set back to D0
-		Store (^D0D3, Local0)
-		if (LEqual (Local0, 3)) {
-			Store (0, ^D0D3)
-		}
-
-		if (LNot (\ISWP())) {
-			// Set PCI 0xB0[14:13]
-			Store (1, ^MB13)
-			Store (1, ^MB14)
-
-			// Set MMIO 0x816C[14,2]
-			Store (1, CLK0)
-			Store (1, CLK1)
-
-			// Clear MMIO 0x8154[31]
-			Store (0, CLK2)
-
-			// Clear MMIO 0x80e0[15]
-			Store (0, AX15)
-
-			// Set PCI CFG offset 0x40[11]
-			Store (1, ^SWAI)
-
-			// Set PCI CFG offset 0x44[13:12]
-			Store (1, ^SAIP)
-		}
-
-		// Put device in D3
-		Store (3, ^D0D3)
-
-		Return ()
 	}
 
 	Name (_PRW, Package(){ 0x6d, 3 })
 
-	// Leave USB ports on for to allow Wake from USB
+	/* Leave USB ports on for to allow Wake from USB */
 
-	Method(_S3D,0)	// Highest D State in S3 State
+	Method (_S3D,0)	/* Highest D State in S3 State*/
 	{
 		Return (3)
 	}
 
-	Method(_S4D,0)	// Highest D State in S4 State
+	Method (_S4D,0)	/* Highest D State in S4 State*/
 	{
 		Return (3)
 	}
-
-	Device (HUB7)
+	Device (HS01)
 	{
-		Name (_ADR, 0x00000000)
-
-		// How many are there?
-		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
-		Device (PRT2) { Name (_ADR, 2) } // USB Port 1
-		Device (PRT3) { Name (_ADR, 3) } // USB Port 2
-		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
-		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
-		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+		Name(_ADR, 0x01)
+	}
+	Device (HS02)
+	{
+		Name(_ADR, 0x02)
+	}
+	Device (HS03)
+	{
+		Name(_ADR, 0x03)
+	}
+	Device (HS04)
+	{
+		Name(_ADR, 0x04)
+	}
+	Device (HS05)
+	{
+		Name(_ADR, 0x05)
+	}
+	Device (HS06)
+	{
+		Name(_ADR, 0x06)
+	}
+	Device (HS07)
+	{
+		Name(_ADR, 0x07)
+	}
+	Device (HS08)
+	{
+		Name(_ADR, 0x08)
+	}
+	Device (HS09)
+	{
+		Name(_ADR, 0x09)
+	}
+	Device (HS10)
+	{
+		Name(_ADR, 0x10)
+	}
+	Device (USR1)
+	{
+		Method(_ADR) { Return (Add(USRA(),0)) }
+	}
+	Device (USR2)
+	{
+		Method(_ADR) { Return (Add(USRA(),1)) }
+	}
+	Device (SS01)
+	{
+		Method(_ADR) { Return (Add(SSPA(),0)) }
+	}
+	Device (SS02)
+	{
+		Method(_ADR) { Return (Add(SSPA(),1)) }
+	}
+	Device (SS03)
+	{
+		Method(_ADR) { Return (Add(SSPA(),2)) }
+	}
+	Device (SS04)
+	{
+		Method(_ADR) { Return (Add(SSPA(),3)) }
+	}
+	Device (SS05)
+	{
+		Method(_ADR) { Return (Add(SSPA(),4)) }
+	}
+	Device (SS06)
+	{
+		Method(_ADR) { Return (Add(SSPA(),5)) }
 	}
 }