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authorLee Leahy <leroy.p.leahy@intel.com>2015-05-12 18:23:27 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2015-07-16 17:24:48 +0200
commit1d14b3e926c15027f9272f1e80b8913fef8cf25d (patch)
treeb3d89ad4bb1b0ea5ac05d1d7dc6cbf26ec93e6c3 /src/soc/intel/skylake/acpi/smbus.asl
parentb000513741d330947bb832a5835378e35bdfb394 (diff)
soc/intel: Add Skylake SOC support
Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/acpi/smbus.asl')
-rw-r--r--src/soc/intel/skylake/acpi/smbus.asl5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/acpi/smbus.asl b/src/soc/intel/skylake/acpi/smbus.asl
index 15bcfde69a..31a5114792 100644
--- a/src/soc/intel/skylake/acpi/smbus.asl
+++ b/src/soc/intel/skylake/acpi/smbus.asl
@@ -3,6 +3,7 @@
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,14 +16,14 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc.
*/
// Intel SMBus Controller 0:1f.3
Device (SBUS)
{
- Name (_ADR, 0x001f0003)
+ Name (_ADR, 0x001f0004)
#ifdef ENABLE_SMBUS_METHODS
OperationRegion (SMBP, PCI_Config, 0x00, 0x100)