diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-05-12 18:19:47 -0700 |
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committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-07-16 17:23:27 +0200 |
commit | b000513741d330947bb832a5835378e35bdfb394 (patch) | |
tree | 0e039f881e195633b53c46424394715fff35558f /src/soc/intel/skylake/acpi/pcie_port.asl | |
parent | 741a0dd89ce67d0fed9a7907bb77ed3ea9afba81 (diff) |
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC
Use the Broadwell implementation as the comparison base for Skylake.
BRANCH=none
BUG=None
TEST=None
Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10340
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake/acpi/pcie_port.asl')
-rw-r--r-- | src/soc/intel/skylake/acpi/pcie_port.asl | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/acpi/pcie_port.asl b/src/soc/intel/skylake/acpi/pcie_port.asl new file mode 100644 index 0000000000..32267461b7 --- /dev/null +++ b/src/soc/intel/skylake/acpi/pcie_port.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Included in each PCIe Root Port device */ + +OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) +Field (RPCS, AnyAcc, NoLock, Preserve) +{ + Offset (0x4c), // Link Capabilities + , 24, + RPPN, 8, // Root Port Number +} |