diff options
author | Duncan Laurie <dlaurie@chromium.org> | 2015-08-27 15:49:12 -0700 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-08 11:16:27 +0000 |
commit | 08112303065bf4d8ebd009c2b5bd1364d4d872ac (patch) | |
tree | 34958b432386205355ac19b6abf3fc774706c9f8 /src/soc/intel/skylake/acpi/pcie.asl | |
parent | 1bfbe7e72a3bb0562e190136a77f889d2cdb81f4 (diff) |
skylake: ACPI: Fix and clean up PCIE _PRT entries
Fix the code for PCIE _PRT entries to use an actual root
port number from the device instead of NVS that was never
initialized from zero.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=build and boot on glados with pci=nomsi to ensure interrupts work
Change-Id: I76ff07d2bf7001aed504558d55cca9e19c692d7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d43392199ec5f37150f2b13732924c47b8dc830c
Original-Change-Id: I1132f1dc47122db08d1b798a259ee9b52a488f5e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295902
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11529
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/acpi/pcie.asl')
-rw-r--r-- | src/soc/intel/skylake/acpi/pcie.asl | 225 |
1 files changed, 153 insertions, 72 deletions
diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl index 7ab78e0b09..52b07dad55 100644 --- a/src/soc/intel/skylake/acpi/pcie.asl +++ b/src/soc/intel/skylake/acpi/pcie.asl @@ -24,56 +24,56 @@ Method (IRQM, 1, Serialized) { /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ - Name (IQAA, Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } }) - Name (IQAP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LNKD, 0 } }) + Name (IQAA, Package () { + Package () { 0x0000ffff, 0, 0, 16 }, + Package () { 0x0000ffff, 1, 0, 17 }, + Package () { 0x0000ffff, 2, 0, 18 }, + Package () { 0x0000ffff, 3, 0, 19 } }) + Name (IQAP, Package () { + Package () { 0x0000ffff, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0000ffff, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0000ffff, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0000ffff, 3, \_SB.PCI0.LNKD, 0 } }) /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ - Name (IQBA, Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } }) - Name (IQBP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LNKA, 0 } }) + Name (IQBA, Package () { + Package () { 0x0000ffff, 0, 0, 17 }, + Package () { 0x0000ffff, 1, 0, 18 }, + Package () { 0x0000ffff, 2, 0, 19 }, + Package () { 0x0000ffff, 3, 0, 16 } }) + Name (IQBP, Package () { + Package () { 0x0000ffff, 0, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0000ffff, 1, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0000ffff, 2, \_SB.PCI0.LNKD, 0 }, + Package () { 0x0000ffff, 3, \_SB.PCI0.LNKA, 0 } }) /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ - Name (IQCA, Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } }) - Name (IQCP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LNKB, 0 } }) + Name (IQCA, Package () { + Package () { 0x0000ffff, 0, 0, 18 }, + Package () { 0x0000ffff, 1, 0, 19 }, + Package () { 0x0000ffff, 2, 0, 16 }, + Package () { 0x0000ffff, 3, 0, 17 } }) + Name (IQCP, Package () { + Package () { 0x0000ffff, 0, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0000ffff, 1, \_SB.PCI0.LNKD, 0 }, + Package () { 0x0000ffff, 2, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0000ffff, 3, \_SB.PCI0.LNKB, 0 } }) /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ - Name (IQDA, Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } }) - Name (IQDP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LNKD, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LNKA, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } }) - - Switch (ToInteger (Arg0)) { - /* PCIe Root Port 1 and 5 */ - Case (Package() { 1, 5 }) { + Name (IQDA, Package () { + Package () { 0x0000ffff, 0, 0, 19 }, + Package () { 0x0000ffff, 1, 0, 16 }, + Package () { 0x0000ffff, 2, 0, 17 }, + Package () { 0x0000ffff, 3, 0, 18 } }) + Name (IQDP, Package () { + Package () { 0x0000ffff, 0, \_SB.PCI0.LNKD, 0 }, + Package () { 0x0000ffff, 1, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } }) + + Switch (ToInteger (Arg0)) + { + Case (Package () { 1, 5, 9 }) { If (PICM) { Return (IQAA) } Else { @@ -81,8 +81,7 @@ Method (IRQM, 1, Serialized) { } } - /* PCIe Root Port 2 and 6 */ - Case (Package() { 2, 6 }) { + Case (Package () { 2, 6, 10 }) { If (PICM) { Return (IQBA) } Else { @@ -90,8 +89,7 @@ Method (IRQM, 1, Serialized) { } } - /* PCIe Root Port 3 and 7 */ - Case (Package() { 3, 7 }) { + Case (Package () { 3, 7, 11 }) { If (PICM) { Return (IQCA) } Else { @@ -99,8 +97,7 @@ Method (IRQM, 1, Serialized) { } } - /* PCIe Root Port 4 and 8 */ - Case (Package() { 4, 8 }) { + Case (Package () { 4, 8, 12 }) { If (PICM) { Return (IQDA) } Else { @@ -120,90 +117,154 @@ Method (IRQM, 1, Serialized) { Device (RP01) { - Name (_ADR, 0x001c0000) + Name (_ADR, 0x001C0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA1)) + Return (IRQM (RPPN)) } } Device (RP02) { - Name (_ADR, 0x001c0001) + Name (_ADR, 0x001C0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA2)) + Return (IRQM (RPPN)) } } Device (RP03) { - Name (_ADR, 0x001c0002) + Name (_ADR, 0x001C0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA3)) + Return (IRQM (RPPN)) } } Device (RP04) { - Name (_ADR, 0x001c0003) + Name (_ADR, 0x001C0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA4)) + Return (IRQM (RPPN)) } } Device (RP05) { - Name (_ADR, 0x001c0004) + Name (_ADR, 0x001C0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA5)) + Return (IRQM (RPPN)) } } Device (RP06) { - Name (_ADR, 0x001c0005) + Name (_ADR, 0x001C0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA6)) + Return (IRQM (RPPN)) } } Device (RP07) { - Name (_ADR, 0x001c0006) + Name (_ADR, 0x001C0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA7)) + Return (IRQM (RPPN)) } } Device (RP08) { - Name (_ADR, 0x001c0007) + Name (_ADR, 0x001C0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA8)) + Return (IRQM (RPPN)) } } + Device (RP09) { Name (_ADR, 0x001D0000) + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + Method (_PRT) { - Return (IRQM (RPA9)) + Return (IRQM (RPPN)) } } @@ -211,9 +272,16 @@ Device (RP10) { Name (_ADR, 0x001D0001) + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + Method (_PRT) { - Return (IRQM (RPAA)) + Return (IRQM (RPPN)) } } @@ -221,19 +289,32 @@ Device (RP11) { Name (_ADR, 0x001D0002) + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + Method (_PRT) { - Return (IRQM (RPAB)) + Return (IRQM (RPPN)) } } Device (RP12) { - Name (_ADR, 0x001D0003) + Name (_ADR, 0x001D0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPAC)) + Return (IRQM (RPPN)) } } - |