diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-08-27 15:49:12 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-08 11:16:27 +0000 |
| commit | 08112303065bf4d8ebd009c2b5bd1364d4d872ac (patch) | |
| tree | 34958b432386205355ac19b6abf3fc774706c9f8 /src/soc/intel/skylake/acpi/globalnvs.asl | |
| parent | 1bfbe7e72a3bb0562e190136a77f889d2cdb81f4 (diff) | |
skylake: ACPI: Fix and clean up PCIE _PRT entries
Fix the code for PCIE _PRT entries to use an actual root
port number from the device instead of NVS that was never
initialized from zero.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=build and boot on glados with pci=nomsi to ensure interrupts work
Change-Id: I76ff07d2bf7001aed504558d55cca9e19c692d7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d43392199ec5f37150f2b13732924c47b8dc830c
Original-Change-Id: I1132f1dc47122db08d1b798a259ee9b52a488f5e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295902
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11529
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/acpi/globalnvs.asl')
| -rw-r--r-- | src/soc/intel/skylake/acpi/globalnvs.asl | 14 |
1 files changed, 1 insertions, 13 deletions
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index b3d1bd2a99..b41fa423c6 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -63,19 +63,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit - RPA1, 32, // 0x30 - 0x33 - Root port address 1 - RPA2, 32, // 0x34 - 0x37 - Root port address 2 - RPA3, 32, // 0x38 - 0x3b - Root port address 3 - RPA4, 32, // 0x3c - 0x3f - Root port address 4 - RPA5, 32, // 0x40 - 0x43 - Root port address 5 - RPA6, 32, // 0x44 - 0x47 - Root port address 6 - RPA7, 32, // 0x48 - 0x4b - Root port address 7 - RPA8, 32, // 0x4c - 0x4f - Root port address 8 - RPA9, 32, // 0x50 - 0x53 - Root port address 9 - RPAA, 32, // 0x54 - 0x57 - Root port address 10 - RPAB, 32, // 0x58 - 0x5b - Root port address 11 - RPAC, 32, // 0x5c - 0x5f - Root port address 12 - DPTE, 8, // 0x60 - Enable DPTF + DPTE, 8, // 0x30 - Enable DPTF /* ChromeOS specific */ Offset (0x100), |