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authorShilpa Sreeramalu <shilpa.sreeramalu@intel.com>2015-06-22 21:48:39 +0530
committerPatrick Georgi <pgeorgi@google.com>2015-08-29 07:31:49 +0000
commita0f515354be6b852eea9e4dfcb99198523e52579 (patch)
treeb64e9211ea4a3d971be6ea564fc72e956d3b490e /src/soc/intel/skylake/acpi/dptf/charger.asl
parent91a192f6d0e5706595e7b2bf4501aec2c8a674f0 (diff)
intel/skylake: Add support for DPTF
This patch adds the ASL files with the DPTF related settings and the thermal devices enabled in the SOC. It also enables the DPTF setting at the global NVS level. BRANCH=None BUG=chrome-os-partner:40855 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also checked the temperature readings of the cooling devices and the thermal zones enumerated in the /sys/class/thermal. Change-Id: I8ad044eaf1ad488fb1682097da83b40d2bede414 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 7624eeca19b4f286b30c3d4ac5b44c5e9619c2c7 Original-Change-Id: I0d92ef42cff5567ea6fc566730588802d8549ce0 Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293391 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/11430 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/acpi/dptf/charger.asl')
-rw-r--r--src/soc/intel/skylake/acpi/dptf/charger.asl79
1 files changed, 79 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/acpi/dptf/charger.asl b/src/soc/intel/skylake/acpi/dptf/charger.asl
new file mode 100644
index 0000000000..bcf5963e18
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/dptf/charger.asl
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+Device (TCHG)
+{
+ Name (_HID, "INT3403")
+ Name (_UID, 0)
+ Name (PTYP, 0x0B)
+ Name (_STR, Unicode("Battery Charger"))
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Return charger performance states defined by mainboard */
+ Method (PPSS)
+ {
+ Return (\_SB.CHPS)
+ }
+
+ /* Return maximum charger current limit */
+ Method (PPPC)
+ {
+ /* Convert size of PPSS table to index */
+ Store (SizeOf (\_SB.CHPS), Local0)
+ Decrement (Local0)
+
+ /* Check if charging is disabled (AC removed) */
+ If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) {
+ /* Return last power state */
+ Return (Local0)
+ } Else {
+ /* Return highest power state */
+ Return (0)
+ }
+
+ Return (0)
+ }
+
+ /* Set charger current limit */
+ Method (SPPC, 1)
+ {
+ /* Retrieve Control (index 4) for specified PPSS level */
+ Store (DeRefOf (Index (DeRefOf (Index
+ (\_SB.CHPS, ToInteger (Arg0))), 4)), Local0)
+
+ /* Pass Control value to EC to limit charging */
+ \_SB.PCI0.LPCB.EC0.CHGS (Local0)
+ }
+
+ /* Initialize charger participant */
+ Method (INIT)
+ {
+ /* Disable charge limit */
+ \_SB.PCI0.LPCB.EC0.CHGD ()
+ }
+}