soc/intel: Replace uses of dev_find_slot()

To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.

Replace this with method that relies on bus topology
that walks the root bus only.

Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 4 insertions, 4 deletions

diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index bd944dac16..910db970f6 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -174,7 +174,7 @@ static int get_cores_per_package(void)
 
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
 	const struct soc_intel_skylake_config *config = dev->chip_info;
 
 	/* Set unknown wake source */
@@ -561,7 +561,7 @@ void generate_cpu_entries(struct device *device)
 
 static unsigned long acpi_fill_dmar(unsigned long current)
 {
-	struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+	struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
 	const bool gfxvten = MCHBAR32(GFXVTBAR) & 1;
 
@@ -584,7 +584,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
 		acpi_dmar_rmrr_fixup(tmp, current);
 	}
 
-	struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB);
+	struct device *const p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB);
 	const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
 	const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1;
 
@@ -695,7 +695,7 @@ void southbridge_inject_dsdt(struct device *device)
 /* Save wake source information for calculating ACPI _SWS values */
 int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
 {
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
 	const struct soc_intel_skylake_config *config = dev->chip_info;
 	struct chipset_power_state *ps;
 	static uint32_t gpe0_sts[GPE0_REG_MAX];