soc/intel/skylake: Add C entry bootblock support

List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34

Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 11 insertions, 7 deletions

diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 30ff7b79de..8ef8ebd09c 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -11,14 +11,18 @@ subdirs-y += ../../../cpu/x86/tsc
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/cache_as_ram.S
+bootblock-y += bootblock/cpu.c
+bootblock-y += bootblock/pch.c
+bootblock-y += bootblock/systemagent.c
+bootblock-y += bootblock/uart.c
+bootblock-y += gpio.c
+bootblock-y += monotonic_timer.c
+bootblock-y += pch.c
+bootblock-y += pcr.c
+bootblock-y += pmutil.c
+bootblock-y += tsc_freq.c
+bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
 
-verstage-y += gpio.c
-verstage-y += memmap.c
-verstage-y += monotonic_timer.c
-verstage-y += pch.c
-verstage-y += pmutil.c
-verstage-y += pcr.c
-verstage-y += tsc_freq.c
 verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
 
 romstage-y += flash_controller.c