soc/intel/skylake: Add support for GSPI controller

Sky Lake PCH contains two GSPI controllers. Using the common GSPI
controller driver implementation for Intel PCH, add support for GSPI
controller buses on Sky Lake/Kaby Lake.

BUG=b:35583330

Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19099
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 4 insertions, 0 deletions

diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index f9c267e435..cb8eb89514 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -19,6 +19,7 @@ bootblock-y += flash_controller.c
 bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c
 bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
 bootblock-y += gpio.c
+bootblock-y += gspi.c
 bootblock-y += monotonic_timer.c
 bootblock-y += pch.c
 bootblock-y += pcr.c
@@ -27,6 +28,7 @@ bootblock-y += spi.c
 bootblock-y += tsc_freq.c
 
 verstage-y += flash_controller.c
+verstage-y += gspi.c
 verstage-y += monotonic_timer.c
 verstage-y += pch.c
 verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
@@ -37,6 +39,7 @@ verstage-y += tsc_freq.c
 
 romstage-y += flash_controller.c
 romstage-y += gpio.c
+romstage-y += gspi.c
 romstage-y += bootblock/i2c.c
 romstage-y += memmap.c
 romstage-y += monotonic_timer.c
@@ -62,6 +65,7 @@ ramstage-y += elog.c
 ramstage-y += finalize.c
 ramstage-y += flash_controller.c
 ramstage-y += gpio.c
+ramstage-y += gspi.c
 ramstage-y += i2c.c
 ramstage-y += igd.c
 ramstage-y += irq.c