soc/intel/skylake: Clean up bootblock/report_platform.c

This patch ensures that all required information for
pch/mch/igd deviceid and revision available in single
stage and make use of local references.

TEST=Build and boot soraka/eve

Change-Id: I6f7f219536831210750a486ee3b3308d6f285451
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22756
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 0 insertions, 5 deletions

diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 4aa76edd74..16f8c065c5 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -16,14 +16,12 @@ bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += gpio.c
 bootblock-y += gspi.c
-bootblock-y += pch.c
 bootblock-y += pmutil.c
 bootblock-y += spi.c
 bootblock-y += lpc.c
 bootblock-$(CONFIG_UART_DEBUG) += uart.c
 
 verstage-y += gspi.c
-verstage-y += pch.c
 verstage-y += pmutil.c
 verstage-y += i2c.c
 verstage-y += spi.c
@@ -34,7 +32,6 @@ romstage-y += gspi.c
 romstage-y += i2c.c
 romstage-y += memmap.c
 romstage-y += me.c
-romstage-y += pch.c
 romstage-y += pei_data.c
 romstage-y += pmc.c
 romstage-y += pmutil.c
@@ -57,7 +54,6 @@ ramstage-y += lockdown.c
 ramstage-y += lpc.c
 ramstage-y += me.c
 ramstage-y += memmap.c
-ramstage-y += pch.c
 ramstage-y += pei_data.c
 ramstage-y += pmc.c
 ramstage-y += pmutil.c
@@ -73,7 +69,6 @@ ramstage-y += vr_config.c
 
 smm-y += elog.c
 smm-y += gpio.c
-smm-y += pch.c
 smm-y += pmutil.c
 smm-y += smihandler.c
 smm-$(CONFIG_UART_DEBUG) += uart.c