diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-05 19:47:47 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-10-26 15:39:40 +0000 |
| commit | 0f91f79447b63b846fe0da770404bf18833f1306 (patch) | |
| tree | bfce597f2a795a1194803afec57666e17dba3508 /src/soc/intel/skylake/Makefile.inc | |
| parent | a9e07f94448650b3a9a27062775c642f8939464b (diff) | |
soc/intel/skylake: drop support for FSP 1.1
This drops support for FSP 1.1 in soc/intel/skylake, after all boards
have been migrated to FSP 2.0, which is backwards compatible.
Any moving of files happens in a follow-up commit to make review easier.
Change-Id: I0dd2eab0edfda0545ff94c3908b8574d5ad830bd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35813
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/skylake/Makefile.inc | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ef741f808b..8174765210 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -37,13 +37,12 @@ romstage-y += memmap.c romstage-y += me.c romstage-y += pmc.c romstage-y += pmutil.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +romstage-y += reset.c romstage-y += spi.c romstage-y += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c -ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c +ramstage-y += chip_fsp20.c ramstage-y += cpu.c ramstage-y += elog.c ramstage-y += finalize.c @@ -59,7 +58,7 @@ ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c -ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += reset.c ramstage-y += sd.c ramstage-y += smmrelocate.c ramstage-y += spi.c @@ -101,13 +100,7 @@ endif CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include - -ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) -CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp11 -CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake -else CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20 -endif # Currently used for microcode path. CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR) |