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authorSubrata Banik <subrata.banik@intel.com>2017-03-14 18:24:47 +0530
committerMartin Roth <martinroth@google.com>2017-03-28 16:40:13 +0200
commit93ebe499d45679a250de780d8a8b73d32d7ea00e (patch)
treec40c6bd71a771df26f94d028718f15ec89444afd /src/soc/intel/skylake/Kconfig
parent01ae11b057e4b15e1fde48c7845f7fbf66a4e948 (diff)
soc/intel/skylake: Clean up code by using common System Agent module
This patch currently contains the SA initialization required for bootblock phase - 1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code. 2. Perform PCIEXBAR programming based on soc configurable PCIEX_LENGTH_xxxMB 3. Use common systemagent header file. Change-Id: I0fa0a60f680b9b00b7f26f1875c553612b123a8e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18566 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/Kconfig')
-rw-r--r--src/soc/intel/skylake/Kconfig6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index ebdcbe3a24..01083723f8 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
select PCIEXP_COMMON_CLOCK
select PCIEXP_CLK_PM
select PCIEXP_L1_SUB_STATE
+ select PCIEX_LENGTH_64MB
select REG_SCRIPT
select RELOCATABLE_MODULES
select RELOCATABLE_RAMSTAGE
@@ -49,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
+ select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_NHLT
@@ -147,10 +149,6 @@ config IED_REGION_SIZE
hex
default 0x400000
-config MMCONF_BASE_ADDRESS
- hex "MMIO Base Address"
- default 0xe0000000
-
config MONOTONIC_TIMER_MSR
def_bool y
select HAVE_MONOTONIC_TIMER