diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2017-05-25 14:12:01 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-06-05 00:32:48 +0200 |
| commit | 842776e1dcb310e889d2ba922be9d7b81a1c2dd0 (patch) | |
| tree | c6276bf0cffe9c8cd436689665b1814757cb92f6 /src/soc/intel/skylake/Kconfig | |
| parent | 1fa16c9cb6c486cdd4b1bcb3734308b28b9c9a22 (diff) | |
soc/intel/skylake: Use Intel timer common code
Use timer code from soc/intel/common. This code removes
monotonic timer refrence w.r.t MSR 24Mhz counter(0x637)
and use tsc timer.
Change-Id: I7fad620b11c9e5db128f646639c79ea58a0a574f
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/Kconfig')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 067e833090..c15e402052 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -62,6 +62,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SATA select SOC_INTEL_COMMON_BLOCK_SMBUS + select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_NHLT @@ -72,6 +73,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC select ACPI_NHLT @@ -158,12 +160,6 @@ config IED_REGION_SIZE hex default 0x400000 -config MONOTONIC_TIMER_MSR - def_bool y - select HAVE_MONOTONIC_TIMER - help - Provide a monotonic timer using the 24MHz MSR counter. - config PCR_BASE_ADDRESS hex default 0xfd000000 |