diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2016-07-18 14:13:52 +0530 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@intel.com> | 2016-07-28 05:14:38 +0200 |
| commit | 68d5d8b28ab399b8dfb8ef6477d25311a319f2d5 (patch) | |
| tree | d1442f94451a2a6ac209ab076d9fe879b9e33bf0 /src/soc/intel/skylake/Kconfig | |
| parent | e3e2bb0a892bc185a52f210bcae15db268c1d034 (diff) | |
soc/intel/skylake: Do cache as ram and prepare for C entry
Enable cache-as-ram and prepare for c entry in bootblock.
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x2A
Credits-to: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I3412216cdf8ef7e952145943d33c3f07949da3c1
Reviewed-on: https://review.coreboot.org/15784
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/Kconfig')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index b86d002bc2..5f12f5bb4a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS select ACPI_NHLT select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE + select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select GENERIC_GPIO_LIB @@ -49,7 +50,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC - select USE_GENERIC_FSP_CAR_INC config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC @@ -100,6 +100,17 @@ config DCACHE_RAM_SIZE The size of the cache-as-ram region required during bootblock and/or romstage. +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 + config EXCLUDE_NATIVE_SD_INTERFACE bool default n |