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authorLin Huang <hl@rock-chips.com>2016-04-08 18:56:20 +0800
committerMartin Roth <martinroth@google.com>2016-05-18 20:23:18 +0200
commit2f7ed8d775153db69d19c77cc79db9b0bb136c70 (patch)
tree774f21bf49a9f5486c9242e9124d1db48e9eaf04 /src/soc/intel/sch/pcie.c
parent95b7a6c6db47bd493a11fa14aa949ddb6788e8db (diff)
rockchip: rk3399: configure emmc clk
Select aclk_emmc and clk_emmc source from GPLL, and both to 198MHz, that is GPLL(594MHz) divided by 3. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot kevin rev1 to chromeos prompt from both emmc and sdcard TEST=LoadKernel faster, more than twice as I measured manually. Change-Id: I2580c43b8c79049c3fe16bbf60bfa1a8e0559948 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 5fd37b66dcce77354e1cafab0d6e806d832c08d2 Original-Change-Id: Id22815b302af3204e0e5537af99c1577b09b0877 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/339152 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14855 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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